MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 777

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

28.3.2.2
The SDHC Status (SDHC_STATUS) register provides information about the status of SDHC operations,
application FIFO status, error conditions, and interrupt status.
When the corresponding interrupt enable is enabled in the SDHC Interrupt Control (SDHC_INT_CNTR)
register for any of these interrupts, the SDHC generates an interrupt request to the CPU. Software needs
to clear the appropriate status bit to clear the corresponding interrupt. The interrupt status bits are cleared
by using a write 1 to clear operation except for the data buffer ready status bits which can only be cleared
by the read or write operation on the data buffer.
Figure 28-3
Freescale Semiconductor
SDHC RESET SDHC Reset. Writes to the SDHC reset bit triggers the reset logic inside the SDHC. Reads from this bit always
START_CLK
STOP_CLK
Field
shows the SDHC Status Register and
SDHC Status
return 0. To reduce power consumption, the clock to the reset logic in the SDHC is off in normal operation.
When there is one access to this register, the clock is enabled for one cycle. To complete the entire reset
period, it needs at least 8 clock pulses to finish the reset cycle. To reset the SDHC module, it is recommended
to write this register with value 0x0008, followed by 0x0009, and then 0x0001 eight times. Refer to
Section 28.5.3.2, “Reset,”
0 No effect.
1 Reset the SDHC module.
Start Clock. Writing a 1 to this bit starts the MMC_SD_CLK clock. Writing a value of 11 on Bits [1:0] of this
register is not allowed.
Note: The SDHC bus clock does not start immediately after writing to this bit. Poll the
0 No effect.
1 Starts the MMC/SD clock.
Stop Clock. Stops the MMC_SD_CLK clock when software writes a value of 1 to this bit. Software should not
stop the MMC_SD_CLK during a transmission period. Writing a value of 11 to bits [1:0] of this register is not
allowed.
Note: A transmission period is the time from when a card data or access related command is submitted to the
Note: The SDHC bus clock does not stop immediately after writing to this bit. Poll the
0 No effect.
1 Stops the MMC/SD clock.
SDHC_STATUS[CARD_BUS_CLK_RUN] bit to ensure the SDHC clock is running.
end of the access operation.
SDHC_STATUS[CARD_BUS_CLK_RUN] bit to ensure the SDHC clock is not running.
Table 28-4. SDHC_STR_STP_CLK field descriptions
MPC5125 Microcontroller Reference Manual, Rev. 2
(
SDHC_STATUS
for detailed information on software reset.
Table 28-5
)
Register
Description
describes the bit fields.
Secure Digital Host Controller (SDHC)
28-5