MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 790

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Secure Digital Host Controller (SDHC)
28-18
INSERTION_EN
BUF_READ_EN Bus Read Enable. This bit controls the buffer read ready interrupt. If the bit is 1, the interrupt is enabled. When
REMOVAL_EN
SDIO_IRQ_EN SDIO Interrupt Enable. Masks the interrupt from the SD I/O card to the SDHC module interrupt.
DAT0_EN
CARD_
CARD_
Field
Card Insertion Enable. Setting this bit enables the card insertion interrupt. Because card detection is through
the value of DAT3 data line, if this card is in 4-bit mode, any data transfers in the DAT3 line causes false card
insertion interrupts to be generated. Card insertion interrupt should be disabled after the first time card
insertion is detected. To avoid false status bit generation during data transfer, card insertion status is masked
by this bit. It should only be enabled after the card is removed from the socket.
The default of this bit is to disable the card insertion interrupt. When this interrupt is detected, write a 1 to the
STATUS[31] bit to clear the card insertion status interrupt.
0 Card insertion interrupt disabled.
1 Card insertion interrupt enabled.
Card Removal Enable. Setting this bit enables the card removal interrupt. Because card detection is through
the value of the DAT3 data line, if this card is in 4-bit mode, the data transfer through the DAT3 line causes
false card removal interrupt to be generated. The card removal interrupt should only be enabled when no
active data transfers exist on the DAT3 line. To avoid the false status bit generation during data transfer, the
card insertion status is masked by this bit.
The default of this bit is to disable the card removal interrupt. When this interrupt is detected, write a 1 to the
STATUS[30] bit to clear the card removal status interrupt.
0 Card removal interrupt disabled.
1 Card removal interrupt enabled.
Note: SDHC uses IPS_CLK to detect the SDIO card interrupt wakeup event when this bit is set.
0 SD I/O interrupt disabled.
1 SD I/O interrupt enabled.
Note: SDHC uses IPS_CLK to detect the SDIO card interrupt wakeup event when this bit is set.
bit is an optional setting for the SDIO bit.
When SDHC preforms data transfer and the SD bus mode is 1-bit mode, set this bit to 0.
0 SD I/O’s Interrupt detection based on DAT[3:0] = b110x.
1 SD I/O’s Interrupt detection based on DAT[3:0] = b1101.
the buffer becomes full during a read operation, an interrupt is generated. Move the data out of the FIFO and
clear the BUF_READ_RDY bit to clear the interrupt.
0 Buffer status interrupt disabled.
1 Buffer status interrupt enabled.
Data Enable. Identifies how the SD I/O interrupt is detected. An interrupt is determined by DAT 1 low, but this
Table 28-13. SDHC_INT_CNTR field descriptions
MPC5125 Microcontroller Reference Manual, Rev. 2
Description
Freescale Semiconductor