MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 997

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

32.8.7
32.8.7.0.1
It is necessary for the DCD software to maintain head and tail pointers for the linked list of dTDs for each
respective queue head. This is necessary because the dQH only maintains pointers to the current working
dTD and the next dTD to be executed. The operations described in the next section for managing dTD
assumes the DCD can use reference for the head and tail of the dTD linked list.
32.8.7.1
Before a transfer can be executed from the linked list, a dTD must be built to describe the transfer. Use the
following procedure for building dTDs.
Allocate 8 32-bit word dTD block of memory aligned to 8 32-bit word boundaries. Example: bit address
4:0 would be equal to 00000.
Write the following fields:
Freescale Semiconductor
1. Initialize first 7 32-bit words to 0.
2. Set the terminate bit to 1.
3. Fill in total bytes with transfer size.
4. Set the interrupt on complete if desired.
5. Initialize the status field with the active bit set to 1 and all remaining status bits set to 0.
6. Fill in buffer pointer page 0 and the current offset to point to the start of the data buffer.
7. Initialize buffer pointer page 1 through page 4 to be one greater than each of the previous buffer
pointer.
Managing Transfers with Transfer Descriptors
Building a Transfer Descriptor
Software Link Pointers
To conserve memory, reserved fields at the end of the dQH can store the
head and tail pointers, but it remains the responsibility of the DCD to
maintain the pointers.
Head Pointer
MPC5125 Microcontroller Reference Manual, Rev. 2
Completed dTDs
Figure 32-76. Software Link Pointers
Endpoint QH
NOTE
current
Queued dTDs
next
Universal Serial Bus Interface with On-The-Go
Tail Pointer
32-169