MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 420

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

General Purpose Timers (GPT)
15.3
The GPT provides eight independent timer channels that perform general purpose I/O, Input Capture,
output compare, pulse width modulation and internal CPU timer functions. An external I/O pin is
associated with each timer channel. A separate 16-bit prescaler and 16-bit internal counter is associated
with each timer channel, thus achieving a range of 32 bits (but only 16-bit resolution). The 16-bit internal
counter is not visible to the user. Thus, its value cannot be modified or read directly by software. In general,
this 16-bit internal counter is used in one of two basic methods. The value of this counter can be captured
upon the occurrence of some event. Then, the contents of the internal counter can be captured again at a
second event. The difference between the two values is the number of prescaled clock counts between the
two events. The second methodology involves adding a value to the internal counter and putting this value
into a compare register. When the counter increments to this calculated value, a predetermined event can
be programmed to occur.
An up/down counter is also implemented. This counter is visible to the user. In general, this counter
increments in response to certain events and decrement in response to other events. The use of this counter
is discussed below.
15.3.1
In this mode, the timer I/O pin is an input. There are two counters used for each timer channel in this mode.
The first counter is the Internal counter, and the second counter is the up/down counter. Once enabled,
when the specified capture event occurs (rising edge, falling edge, either edge, or pulse—two consecutive
edges), the internal counter value is latched in the status register. If enabled, a CPU interrupt is generated.
The input capture function has the following submodes:
These modes are controlled by the ICM bits described in
15.3.1.1
Only the internal counter is active in this mode. The IC Mode is selected by setting the ICM field of the
GPT_MODE register associated with a particular timer channel to 0b00. In this mode, the ICT bits of the
GPT_MODE are used to configure the Timer Channel pin as an input and to respond to any transition, a
positive transition, a negative transition, or a pulse consisting of two consecutive edges. In the cases of any
transition, positive transition or negative transition, the value of the internal counter is latched into the
CAPTURE field of the GPT Status Register associated with the particular timer channel. If enabled by the
INTEN bit of the GPT_MODE register for a particular channel, an interrupt to the CPU is generated.
15.3.1.2
When a timer channel is programmed to use the UP Mode, both the up/down counter and internal counter
are active. The up/down counter is incremented by one each time an Input Capture Event, as defined by
15-10
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Normal input capture mode
Up mode
Up down mode
Rotary mode
Functional Description
Input Capture Mode
Normal Input Capture Mode (IC MODE)
UP Submodule
MPC5125 Microcontroller Reference Manual, Rev. 2
Section 15.2.1, “Register Descriptions.”
Freescale Semiconductor