MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 822

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Software Watchdog Timer (WDT)
Although most software disciplines permit or even encourage the watchdog concept, some systems require
a selection of timeout periods. For this reason, the WDT must provide a selectable range for the timeout
period.
In
SWTC is loaded into a 16-bit decrementer clocked by the system XTAL clock. An additional
divide-by-65,536 prescaler value is used when needed.
The decrementer begins counting when loaded with a value from SWTC. After the timer reaches 0x000,
a software watchdog expiration request is issued to the reset or MCP control logic. Upon reset, the SWTC
field is set to the maximum value and is again loaded into the software watchdog count register
(WDT_SWCRR), starting the process over. When a new value is loaded into SWTC, the WDT is not
updated until the servicing sequence is written to the WDT_SWSRR. If WDT_SWCRR[SWEN] is loaded
with 0, the modulus counter does not count.
29.3.2
The WDT unit can operate in the following modes:
29-6
Figure
•
•
System XTAL
WDT enable/disable mode
If the WDT is not needed, the user can disable it. The WDT_SWCRR[SWEN] bit enables the
watchdog timer. It should be cleared by software after a system reset to disable the WDT. When it
is disabled, the watchdog counter and prescaler counter are held in a stopped state.
— WDT enable mode (WDT_SWCRR[SWEN] = 1)
— WDT disable mode (WDT_SWCRR[SWEN] = 0)
WDT reset/interrupt output mode
Without periodic software servicing, the WDT times out and issues a reset or a nonmaskable MCP
interrupt.
According to WDT_SWCRR[SWRI] programming, WDT causes a hardware reset or MCP
interrupt to the core.
Figure 29-5
Clock
29-5, the range is determined by the value of the WDT_SWCRR[SWTC] field. The value in
This is the default value after soft reset.
If the WDT is not needed, the user must clear WDT_SWCRR[SWEN] to disable it.
Modes of Operation
WDT_SWCRR[SWEN]
shows how to manage this need.
Disable
Figure 29-5. Software Watchdog Timer Functional Block Diagram
Clock
MPC5125 Microcontroller Reference Manual, Rev. 2
65,536
Divider
WDT_SWCRR[SWPR]
WDT_SWCRR[SWTC]
16-Bit Decrementer
SWSRR[WS]
WDT_SWCNR
Service
Reload
Timeout
Freescale Semiconductor
WDT_SWCRR[SWRI]
or MCP
Reset
Event
Logic