MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 716

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Programmable Serial Controller (PSC)
25.5.2
After reset, all PSCs are in UART mode. The PSCs can be applied to one of the codec modes by writing
the appropriate value to the SICR register. The other values should be initialized at the same time. During
codec mode, the PSC can connect to codec interfaces with 8, 12,16, 20, 24, or 32 bit data. For all these
modes, the PSC can be programmed to behave as a normal soft modem interface, SPI, ESAI, or I2S
interface. The PSC codec supports all these modes the master mode (PSC drive the BCLK and FrameSync
signal) or slave mode (PSC receive the BCLK and FrameSync signals) functionality. Independently from
the mode (master or slave), the PSC can provide a MCLK (master clock) for an external codec device. This
behavior eliminates the need for an external crystal for the external codec device.
simplified block diagram for the PSC codec mode. The important register to configure the PSC for codec
mode are:
25-38
•
•
•
•
SICR register—select the codec mode
For master mode:
— select and enable MCLK divider
— CCR—select BCLK and FrameSync frequency
— CTUR—select FrameSync width
CR register—enable or disable receiver and transmitter
MR2 register
PSC in Codec Mode
The interface to the FIFO controller (FIFOC) supports 8, 16, and 32 bit
access only. The data must be right-aligned in the FIFO, as shown in
Table
25-29.
Code mode
12-bit
16-bit
20-bit
24-bit
32-bit
8-bit
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 25-29. FIFO Interface Support
Access to the FIFO
16-bit
16-bit
32-bit
32-bit
32-bit
8-bit
NOTE
12-bit, right assigned
20-bit, right assigned
24-bit, right assigned
used data
all 16-bit
all 32-bit
all 8-bit
Figure 25-44
Freescale Semiconductor
shows a