MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 148

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Byte Data Link Controller (BDLC)
The TMIFR0 bit is used to request the BDLC module to transmit the byte in the BDLC Data Register as
the first byte of a multiple byte IFR without CRC. Response IFR bytes are subject to J1850 message length
maximums.
After the byte in the BDLC Data Register has been loaded into the transmit shift register, the TDRE flag
is set in the BDLC_DLCBSVR register, similar to the main message transmit sequence. If the interrupt
enable bit (IE in the BDLC_DLCBCR1 register) is set, an interrupt request from the BDLC module is
generated. The programmer should then load the next byte of the IFR into the BDLC Data Register for
transmission. When the last byte of the IFR has been loaded into the BDLC Data Register, the programmer
should set the TEOD bit in the BDLC Control Register 2. This instructs the BDLC to transmit an EOD
symbol, indicating the end of the IFR portion of the message frame. The BDLC module does not append
a CRC.
However, if the programmer wishes to transmit a single byte, the programmer should load the byte into
the BDLC Data Register and then set the TMIFR0 bit before the EOD symbol has been received. Once the
TDRE flag is set and interrupt occurs (if enabled), the programmer should then set the TEOD bit in BDLC
Control Register 2. This results in the byte in the BDLC Data Register being the only byte transmitted.
Set the TMIFR0 bit before the EOF following the main part of the message frame is received, or no IFR
transmit attempts is made for the current message. If another node transmits an IFR to this message, the
user must set the TMIFR0 bit before the normalization bit is received or no IFR transmit attempts are made
for the message. If another node does transmit a successful IFR or a reception error occurs, the TMIFR0
bit is cleared. If not, the IFR is transmitted after the EOD of the next received message.
If a transmitter underrun error occurs during transmission (caused by the programmer not writing another
byte to the BDLC Data Register following the TDRE flag being set) the BDLC module automatically
disables the transmitter after the byte currently in the shifter plus two extra 1-bits have been transmitted.
The receiver picks this up as an framing error and relay it in the State Vector Register as an invalid symbol
error. The TMIFR0 bit is also cleared.
If a loss of arbitration occurs when the BDLC module is transmitting a multiple byte IFR without CRC,
the BDLC module goes to the loss of arbitration state, set the appropriate flag and cease transmission. The
TMIFR0 bit is cleared and no attempt is made to retransmit the byte in the BDLC Data Register. If loss of
arbitration occurs in the last bit of the IFR byte, two additional one bits (a passive long followed by an
active short) is sent out.
6-12
The extra logic is an enhancement to the J1850 protocol that forces a byte
boundary condition fault. This helps prevent noise on the J1850 bus from
corrupting a message.
The extra logic is an enhancement to the J1850 protocol that forces a byte
boundary condition fault. This helps prevent noise on the J1850 bus from
corrupting a message.
MPC5125 Microcontroller Reference Manual, Rev. 2
NOTE
NOTE
Freescale Semiconductor