MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 890

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Universal Serial Bus Interface with On-The-Go
32.5.3.2
doublewords one through eight are eight slots of transaction control and status. Each transaction
description includes:
The host controller uses the information in each transaction description plus the endpoint information
contained in the first three doublewords of the buffer page pointer list to execute a transaction on the USB.
32.5.3.3
Doublewords 9-15 of an isochronous transaction descriptor are nominally page pointers (4K aligned) to
the data buffer for this transfer descriptor. This data structure requires the associated data buffer to be
contiguous (relative to virtual memory), but allows the physical memory pages to be non-contiguous.
Seven page pointers are provided to support the expression of eight isochronous transfers. The seven
32-62
Transaction n
Transaction n
•
•
•
Length
31–28
Status
27–16
14–12
Offset
Field
11–0
IOC
PG
15
Status results field
Transaction length (bytes to send for OUT transactions and bytes received for IN transactions).
Buffer offset. The PG and transaction n offset fields are used with the buffer pointer list to construct
the starting buffer address for the transaction.
iTD Transaction Status and Control List
iTD Buffer Page Pointer List (Plus)
This field records the status of the transaction executed by the host controller for this slot. This field is a bit
vector with the following encoding:
31 Active. Set by software to enable the execution of an isochronous transaction by the host controller. When
30 Data Buffer Error. Set by the host controller during status update to indicate that the host controller is unable
29 Babble Detected. Set by the host controller during status update when babble is detected during the
28 Transaction Error (XactErr). Set by the host controller during status update in the case where the host did
For an OUT, this field is the number of data bytes the host controller sends during the transaction. The host
controller is not required to update this field to reflect the actual number of bytes transferred during the transfer.
For an IN, the initial value of the endpoint to deliver. During the status update, the host controller writes back
this field with the number of bytes the host expects to receive. The value in this register is the actual byte count
(for example, 0 zero length data, 1 one byte, 2 two bytes, etc.). The maximum value this field may contain is
0xC00 (3072).
Interrupt on complete. If this bit is set, it specifies that when this transaction completes, the host controller
should issue an interrupt at the next interrupt threshold.
These bits are set by software to indicate which of the buffer page pointers the offset field in this slot should be
concatenated to produce the starting memory address for this transaction. The valid range of values for this
field is 0 to 6.
This field is a value that is an offset, expressed in bytes, from the beginning of a buffer. This field is
concatenated onto the buffer page pointer indicated in the adjacent PG field to produce the starting buffer
address for this transaction.
the transaction associated with this descriptor is completed, the host controller sets this bit to 0 indicating
that a transaction for this element should not be executed when it is next encountered in the schedule.
to keep up with the reception of incoming data (overrun) or is unable to supply data fast enough during
transmission (underrun). If an overrun condition occurs, no action is necessary.
transaction generated by this descriptor.
not receive a valid response from the device (Time-out, CRC, Bad PID, etc.). This bit may only be set for
isochronous IN transactions.
Table 32-45. iTD Transaction Status and Control
MPC5125 Microcontroller Reference Manual, Rev. 2
Description
Freescale Semiconductor