MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 969

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Universal Serial Bus Interface with On-The-Go
During H-Frame X+2, micro-frame 0, the host controller detects that siTD
's back pointer [T] bit is zero,
X+2
saves the state of siTD
and fetches siTD
. As described above, it executes another split transaction,
X+2
X+1
receives an MDATA response, updates the transfer state, but does not modify the active bit. The host
controller returns to the context of siTD
, and traverses it's next pointer without any state change updates
X+2
to siTD
.
X+2
During H-Frame X+2, micro-frame 1, the host controller detects siTD
's S-mask[0] bit is zero, saves
X+2
the state of siTD
and fetches siTD
. It executes another complete-split transaction, receives a
X+2
X+1
DATA0 response, updates the transfer state and clears the Active bit. It returns to the state of siTD
and
X+2
changes its SplitXState to Do Start Split. At this point, the host controller is prepared to execute start-splits
for siTD
when it reaches micro-frame 4.
X+2
32.6.12 Host Controller Pause
When the host controller's HCHalted bit in the USB_USBSTS register is a zero, the host controller is
sending SOF (Start OF Frame) packets down all enabled ports. When the schedules are enabled, the EHCI
host controller accesses the schedules in main memory each micro-frame. This constant pinging of main
memory is known to create CPU power management problems for mobile systems. Specifically, mobile
systems aggressively manage the state of the CPU, based on recent history usage. In the more aggressive
power saving modes, the CPU can disable its caches. Current PC architectures assume that bus-master
accesses to main memory must be cache-coherent. So, when bus masters are busy touching memory, the
CPU power management software can detect this activity over time and inhibit the transition of the CPU
into its lowest power savings mode. USB controllers are bus-masters and the frequency at which they
access their memory-based schedules keeps the CPU power management software from placing the CPU
into its lowest power savings state.
USB Host controllers don't access main memory when they are suspended. However, there are a variety
of reasons why placing the USB controllers into suspend won't work, but they are beyond the scope of this
document. The base requirement is that the USB controller needs to be kept out of main memory, while at
the same time, the USB bus is kept from going into suspend.
EHCI controllers provide a large-grained mechanism that can be manipulated by system software to
change the memory access pattern of the host controller. System software can manipulate the schedule
enable bits in the USB_USBCMD register to turn on/off the scheduling traversal. A software heuristic can
be applied to implement an on/off duty cycle that allows the USB to make reasonable progress and allow
the CPU power management to get the CPU into its lowest power state. This method is not intended to be
applied at all times to throttle USB, but should only be applied in specific configurations and usage loads.
For example, when only a keyboard or mouse is attached to the USB, the heuristic could detect times when
the USB is attempting to move data only infrequently and can adjust the duty cycle to allow the CPU to
reach its low power state for longer periods of time. Similarly, it could detect increases in the USB load
and adjust the duty cycle appropriately, even to the point where the schedules are never disabled. The
assumption here is that the USB is moving data and the CPU is required to process the data streams.
To provide a complete solution for the system, the companion host controllers should also provide a similar
method to allow system software to inhibit the companion host controller from accessing it's shared
memory based data structures (schedule lists or otherwise).
MPC5125 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor
32-141