MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 889

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

1
2
32.5.3.1
The first doubleword of an iTD is a pointer to the next schedule data structure.
Freescale Semiconductor
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Pointer
Host controller read/write; all others read-only.
These fields may be modified by the host controller if the I/O field indicates an OUT.
Field
31–5
Status
Status
Status
Status
Status
Status
Status
Status
Link
Typ
4,3
2,1
0
T
1
1
1
1
1
1
1
1
These bits correspond to memory address signals [31:5], respectively. This field points to another isochronous
transaction descriptor (iTD/siTD) or queue head (QH).
Reserved. These bits are reserved and their value has no effect on operation. Software should initialize this field to
0.
controller to perform the proper type of processing on the item after it is fetched. Value encodings are:
00 iTD (isochronous transfer descriptor)
01 QH (queue head)
10 siTD (split transaction isochronous transfer descriptor
11 FSTN (frame span traversal node)
Terminate
1 Link Pointer field is not valid.
0 Link Pointer field is valid.
This field indicates to the host controller whether the item referenced is an iTD, siTD, or a QH. This allows the host
Next Link Pointer
Transaction 0 Length
Transaction 1 Length
Transaction 2 Length
Transaction 3 Length
Transaction 4 Length
Transaction 5 Length
Transaction 6 Length
Transaction 7 Length
Buffer Pointer (Page 0)
Buffer Pointer (Page 1)
Buffer Pointer (Page 2)
Buffer Pointer (Page 3)
Buffer Pointer (Page 4)
Buffer Pointer (Page 5)
Buffer Pointer (Page 6)
Figure 32-46. Isochronous Transaction Descriptor (iTD)
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 32-44. Next Schedule Element Pointer
Next Link Pointer
1
1
1
1
1
1
1
1
IOC
IOC
IOC
IOC
IOC
IOC
IOC
IOC
15
Description
14 13 12
PG
PG
PG
PG
PG
PG
PG
PG
2
2
2
2
2
2
2
2
I/O
11
EndPt
10
Universal Serial Bus Interface with On-The-Go
9
Transaction 0 Offset
Transaction 1 Offset
Transaction 2 Offset
Transaction 3 Offset
Transaction 4 Offset
Transaction 5 Offset
Transaction 6 Offset
Transaction 7 Offset
8
Maximum Packet Size
Reserved
R
7
Reserved
Reserved
Reserved
Reserved
6
5
Device Address
4
00
3
2
2
2
2
2
2
2
2
2
Typ
1
Mult
T 0x00
0
0x0C
0x1C
0x2C
0x3C
0x04
0x08
0x10
0x14
0x18
0x20
0x24
0x28
0x30
0x34
0x38
offset
32-61