MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 35

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chapter 2
System Configuration and Memory Map
(XLBMEN + Mem Map)
2.1
The System Configuration and Memory Map chapter describes the memory map of the MPC5125 and also
details information on setting up the system configuration. The memory map is described by 13 local
access windows. Some of these memory access windows point to various blocks of the 32-bit memory
address space while other memory access windows point to specific peripheral modules. A list of the local
access windows is shown in
window are presented in
2.2
2.2.1
The MPC5125 provides a flexible local memory map. The local memory map refers to the 32-bit address
space seen by the processor as it accesses memory and I/O space. Internal DMA engines also see this same
local memory map. All memory accessed by the MPC5125 DDR SDRAM and LocalPlus controllers exists
in this memory map, as do all memory-mapped configuration, control, and status registers.
The local memory map of the MPC5125 is defined by a set of 13 local access windows. Each of these
windows maps a region of memory to a particular target interface, such as the DDR SDRAM controller.
The LPC windows do not perform any address translation. Each local access window is assigned to a
specific target interface as specified in
Local Access Windows are defined in several different ways. For instance, Local Access Window 0 is used
for the configuration registers which include the IMMRBAR register and the base address for registers in
the various peripheral modules. The block size for Local Access Window 0 is fixed at 1 MB. Local Access
Windows 1–9 are specified by the Start_Addr and Stop_Addr fields of the respective LocalPlus Access
Window Registers for Chip Select Boot and Chip Selects 0–7. The DDR SDRAM window base address
and size is specified by the DDR Local Access Window Base Address Register and the size of the window
is specified by the DDR Local Access Window Attributes Register. Window 11 is used for the SRAM
module. The SRAM module base address register is located at IMMRBAR + 0xC4. The block size is fixed
at 32 KB; however, a 256 KB memory window is reserved for SRAM. Window 12 is used for the NAND
Flash Controller. The NAND Flash Controller base address register is located at IMMR + 0xC8. The block
size is fixed at 1 MB.
Freescale Semiconductor
Introduction
Memory Map and Register Definition
Local Memory Map Overview and Example
Table
Table
MPC5125 Microcontroller Reference Manual, Rev. 2
2-2.
2-1. The registers that set the base address and size of each local access
Table
2-1.
2-1