MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 127

IC MCU 32BIT E300 324TEPBGA

MPC5125YVN400

Manufacturer Part Number
MPC5125YVN400
Description
IC MCU 32BIT E300 324TEPBGA
Manufacturer
Freescale Semiconductor
Series
MPC51xxr

Specifications of MPC5125YVN400

Core Processor
e300
Core Size
32-Bit
Speed
400MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, USB OTG
Peripherals
DMA, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.33 V ~ 1.47 V
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
324-PBGA
Processor Series
MPC51xx
Core
e300
Data Bus Width
32 bit
Development Tools By Supplier
TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
Maximum Clock Frequency
400 MHz
Operating Supply Voltage
1.4 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Data Ram Size
32 KB
I/o Voltage
3.3 V
Interface Type
CAN, I2C
Minimum Operating Temperature
- 40 C
Program Memory Size
32 bit
Cpu Speed
400MHz
Embedded Interface Type
CAN, I2C, SPI, UART, USB
Digital Ic Case Style
TEPBGA
No. Of Pins
324
Rohs Compliant
Yes
Cpu Family
MPC5xx
Device Core Size
32b
Frequency (max)
400MHz
Total Internal Ram Size
32KB
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
324
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MPC5125YVN400
Manufacturer:
Freescale Semiconductor
Quantity:
135
Part Number:
MPC5125YVN400
Manufacturer:
LTC
Quantity:
29
Part Number:
MPC5125YVN400
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
5.3.1.19
The MSCAN1 clock control register shown in
ratio, the MSCAN1 divider enable, and the MSCAN1 divider clock source.
fields of M1CCR.
Freescale Semiconductor
Address: Base + 0x54
Address: Base + 0x58
DLY_NUM
Reset
Reset
Reset
Reset
CLK_INV
Field
W
W
W
W
R
R
R
R
MSCAN1_
DLY_NUM
CLK_SRC
16
16
0
0
0
1
0
0
0
MSCAN1 Clock Control Register (M1CCR)
Number of CSB_CLK cycles delay added to pixel clock output to pad compare pixel clock to DIU.
00 0 cycle delay.
01 2 cycles delay.
10 4 cycles delay.
11 6 cycles delay.
Pixel Clock Inversion
0 The pixel clock to pad is the same as the one to the DIU. The DLY_NUM bitfield specifies s the delay CSB
1 The pixel clock to pad is inverted from the one to the DIU. The DLY_NUM bitfield specifies s the delay CSB
17
17
0
0
0
1
0
1
1
cycles added to it.
cycles added to it.
18
18
0
0
0
1
0
0
2
2
Figure 5-24. MSCAN1 Clock Control Register (M1CCR)
19
19
0
0
0
1
0
0
3
3
Figure 5-23. DIU Clock Config Register (DCCR)
MPC5125 Microcontroller Reference Manual, Rev. 2
20
20
Table 5-23. DCCR field descriptions
4
0
0
0
4
1
0
0
21
21
0
0
0
1
0
0
5
5
MSCAN1_CLK_DIV
22
Figure 5-24
22
0
0
0
1
0
0
6
6
CLK_
INV
23
23
0
0
0
1
0
0
7
7
Description
24
24
8
0
0
0
0
controls the MSCAN1 source clock divider
8
1
0
0
25
25
9
0
0
0
0
9
1
0
0
10
26
10
26
0
0
0
0
1
0
0
Table 5-24
11
27
11
27
0
0
0
0
1
0
0
Clocks and Low-Power Modes
12
28
12
28
0
0
0
0
1
0
0
Access: User read/write
Access: User read/write
defines the bit
13
29
13
29
0
0
0
0
1
0
0
14
30
14
30
0
0
0
0
1
0
0
AN1_
MSC
EN
15
31
15
31
5-27
0
0
0
0
0
0
0

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