MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 624

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

MSCAN
22.4.8.1
The Power Architecture can request the MSCAN to enter this low power mode by asserting the SLPRQ
bit in the CANCTL0 register. The time when the MSCAN enters sleep mode depends on a
fixed-synchronization delay and its current activity:
If sleep mode is active, the SLPRQ and SLPAK bits are set
use SLPAK as a handshake indication for the request (SLPRQ) to go into sleep mode.
When in sleep mode (SLPRQ = 1 and SLPAK = 1), the MSCAN stops its internal clocks. However, clocks
that allow register accesses from the Power Architecture side continue to run.
22-46
•
•
•
If there are one or more message buffers scheduled for transmission (TXEx = 0), the MSCAN
continues to transmit until all transmit message buffers are empty (TXEx = 1, transmitted
successfully or aborted) and then goes into sleep mode.
If the MSCAN is receiving, it continues to receive and goes into sleep mode as soon as the CAN
bus next becomes idle.
If the MSCAN is neither transmitting nor receiving, it immediately goes into sleep mode.
1
MSCAN Sleep Mode
The application software must avoid setting up a transmission (by clearing
one or more TXEx flag[s]) and immediately request sleep mode (by setting
SLPRQ). It depends on the exact sequence of operations whether the
MSCAN starts transmitting or goes into sleep mode directly.
X means “don’t care”
Power Architecture Clock Domain
Power Architecture
Sleep Request
SLPRQ = 0
SLPAK = 0
Normal
SLPAK
Flag
Figure 22-39. Sleep Request/Acknowledge Cycle
MPC5125 Microcontroller Reference Manual, Rev. 2
SLPRQ
sync.
SLPAK
Table 22-33. MSCAN Operating Modes
Power Down (Power
Architecture enters
deep sleep)
SLPRQ = X
SLPAK = X
MSCAN Mode
NOTE
SYNC
SYNC
SLPRQ = 1
SLPAK = 1
CAN Clock Domain
(Figure
Sleep
sync.
SLPRQ
SLPAK
22-39). The application software must
MSCAN
in Sleep Mode
SLPRQ = X
(CANE = 0)
SLPRQ
Flag
SLPAK = X
Freescale Semiconductor
1