MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 675

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

this case if enabled (PMC_PMCER[INT1], see
(PMC_PMCER)”).
24.3.5
The system provides a low-power consumption mode where the e300 core enters sleep mode. The system
oscillator, system PLL, and e300 PLL are all powered down and disabled. While the module enters this
mode, all internal functional units, except the real-time clock (RTC), are disabled. As the clocks are static,
the current draw of the device is reduced to leakage level. The internal state of the device is maintained in
deep sleep as long as power is maintained. The real-time clock (RTC) is not disabled in deep sleep mode.
If the RTC is used, that portion of the chip continues consuming power in deep sleep mode.
In this mode, bus snooping is disabled. The core waits unit the snoop bus is idle before entering deep sleep
mode.
The DRAM is put into self-refresh mode during deep sleep mode. It is required that the DRAM controller
is configured for putting the DRAM in self-refresh mode upon receipt of the request.
To enter deep sleep mode, the POW bit in the e300 MSR register must be set, then the DSM bit in the
PMC_PMCCR register must be set, before setting the sleep bit in an e300 system register (HID0[10] = 1).
An power-on reset, or an asynchronous interrupt from GPIO, RTC or one of the CAN modules (which
occurs when a data transition occurs on the serial input) can be used to bring the module back to the
full-power state from deep sleep mode. No clock is required to trigger the wake up process in the case of
the GPIO interrupt or the CAN module interrupt. On reception of a wakeup signal from GPIO, RTC, or
MSCAN, PMC enables the system oscillator and PLLs in turn and waits for the oscillator to stable and
PLLs to lock. After the system clocks are back to full-power mode, the interrupt from GPIO, RTC and
MSCAN may bring the e300 core back to the full-power state. The wakeup time is listed in
During deep sleep mode, state of all peripherals is frozen. All state and data is retained in internal registers,
but the peripherals stop reacting on triggers from outside (e.g. a UART does not see incoming data any
more). Reinitialization may be needed after leaving deep sleep mode.
Reset is not needed after deep sleep mode.
24.3.6
This mode can be used to change the core PLL setting. To change it, write the new setting to the shadow
register (PMC_PMCSR) in PMC module, and then set the CCM bit in the PMC_PMCCR register. Because
the core PLL needs relock, the core must enter sleep mode.
To enter core PLL change mode, the POW bit in the e300 MSR register must be set, then the CCM bit in
the PMC_PMCCR register must be set, before setting the sleep bit in an e300 system register
(HID0[10] = 1).
Freescale Semiconductor
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Reinitialization is not needed if the peripheral does not need to resynchronize to an external
interface, or if the resynchronization can be done without reinitialization
Reinitialization is needed if the peripheral requires it to sync again with an external interface.
Deep Sleep Mode
Core PLL Change Mode
MPC5125 Microcontroller Reference Manual, Rev. 2
Section 24.2.2.2, “PMC Event Register
Power Management Control Module (PMC)
Table
24-8.
24-11