MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 232

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Direct Memory Access (DMA)
9.2.1.2
The DMA Error Status (DMAES) register provides information concerning the last recorded channel error.
Channel errors can be caused by a configuration error (an illegal setting in the transfer control descriptor
or an illegal priority register setting in fixed arbitration mode) or an error termination to a bus master read
or write cycle.
A configuration error is caused when the starting source or destination address, source or destination
offsets, minor loop byte count and the transfer size represent an inconsistent state. The addresses and
offsets must be aligned on transfer_size boundaries, and the minor loop byte count must be a multiple of
the source and destination transfer sizes. All source reads and destination writes must be configured to the
natural boundary of the programmed transfer size respectively. In fixed arbitration mode, a configuration
error is caused by any two channel priorities being equal within a group, or any group priority levels being
equal among the groups. All channel priority levels within a group must be unique and all group priority
levels among the groups must be unique when fixed arbitration mode is enabled. If a scatter/gather
operation is enabled upon channel completion, a configuration error is reported if the scatter/gather
address (DLAST_SGA) is not aligned on a 32-byte boundary. If minor loop channel linking is enabled
upon channel completion, a configuration error is reported when the link is attempted if the
TCD.CITER.E_LINK bit does not equal the TCD.BITER.E_LINK bit. All configuration error conditions
except scatter/gather and minor loop link error are reported as the channel is activated and asserts an error
interrupt request, if enabled. A scatter/gather configuration error is reported when the scatter/gather
operation begins at major loop completion when properly enabled. A minor loop channel link
configuration error is reported when the link operation is serviced at minor loop completion.
If a system bus read or write is terminated with an error, the data transfer is stopped and the appropriate
bus error flag set. In this case, the state of the channel’s transfer control descriptor is updated by the
DMA_ENGINE with the current source address, destination address, and current iteration count at the
point of the fault. When a system bus error occurs, the channel is terminated after the read or write
transaction already pipelined after errant access, has completed. If a bus error occurs on the last read prior
9-12
GRP0PRI
ERGA
EDBG
ERCA
Field
DMA Error Status (DMAES)
Channel Group 0 Priority. Group 0 priority level when fixed priority group arbitration is enabled.
Enable Round Robin Group Arbitration
0 Fixed priority arbitration is used for selection among the groups.
1 Round robin arbitration is used for selection among the groups.
Enable Round Robin Channel Arbitration
0 Fixed priority arbitration is used for channel selection within each group.
1 Round robin arbitration is used for channel selection within each group.
Enable Debug
0 Ignore DMA debug input.
1 Setting of TEST DMADBG bit, or e300 breakpoint causes the DMA to stall the start of a new channel.
Executing channels are allowed to complete. Channel execution resumes when TEST DMADBG bit is
cleared, e300 resumes execution, or the EDBG bit is cleared.
Table 9-4. DMACR field descriptions (continued)
MPC5125 Microcontroller Reference Manual, Rev. 2
Description
Freescale Semiconductor