MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 968

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Universal Serial Bus Interface with On-The-Go
machine must be managed across these time-oriented data structures. This means that system software
must correctly describe the scheduling of split-transactions across more than one data structure.
The host controller must make the appropriate state transitions at the appropriate times, in the correct data
structures.
For example,
full-speed isochronous data stream.
This example shows the first three siTDs for the transaction stream. Because this is the case-2a frame-wrap
case, S-masks of all siTDs for this endpoint have a value of 0x10 (a one bit in micro-frame 4) and C-mask
value of 0xC3 (one-bits in micro-frames 0,1, 6 and 7). Additionally, software ensures that the back pointer
field of each siTD references the appropriate siTD data structure (and the Back Pointer T-bits are cleared).
The initial SplitXState of the first siTD is Do Start Split. The host controller visits the first siTD eight times
during frame X. The C-mask bits in micro-frames 0 and 1 are ignored because the state is Do Start Split.
During micro-frame 4, the host controller determines it can run a start-split (and does) and changes
SplitXState to Do Complete Split. During micro-frames 6 and 7, the host controller executes
complete-splits. The siTD for frame X+1 has its SplitXState initialized to Do Complete Split. As the host
controller continues to traverse the schedule during H-Frame X+1, it visits the second siTD eight times.
During micro-frames 0 and 1, it detects that it must execute complete-splits.
During H-Frame X+1, micro-frame 0, the host controller detects that siTD
zero, saves the state of siTD
transaction state of siTD
written back to siTD
SplitXState in siTD
start-split for siTD
(transaction-complete is defined in
complete-splits have been executed, the host controller changes siTD
and naturally skips the remaining scheduled complete-split transactions. For this example, siTD
not receive a DATA0 response until H-Frame X+2, micro-frame 1.
32-140
siTDX
X + 1
X + 3
X + 2
X
#
C-Mask
C-Mask
C-Mask
C-Mask
S-Mask
S-Mask
S-Mask
S-Mask
Masks
Table 32-80
Table 32-80. Example Case 2a - Software Scheduling siTDs for an IN Endpoint
X+1
X+1
X
. The host controller retains the fact that siTD
when it reaches micro-frame 4. If the split-transaction completes early
to Do Start Split. At this point, the host controller is prepared to execute the
X
0
1
1
1
. If the siTD
illustrates a few frames worth of scheduling required to schedule a case 2a
X+1,
MPC5125 Microcontroller Reference Manual, Rev. 2
and fetches siTD
1
1
1
1
Periodic Isochronous - Do Complete
X
split transaction is complete, siTD's active bit is cleared and results
2
Repeats previous pattern
Micro-Frames
3
X
. It executes the complete split transaction using the
4
1
1
1
5
X
X
[SplitXState] to Do Start Split early
is retired and transitions the
6
1
1
1
Split), before all the scheduled
X+1
7
1
1
1
's back pointer [T] bit is a
Do Complete Split
Do Complete Split
Do Start Split
Do Complete Split
Freescale Semiconductor
InitialSplitXState
X+1
does