MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 168

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Byte Data Link Controller (BDLC)
6.4.2.11.3
A symbol error is detected when an abnormal (invalid) symbol is detected in a message being received
from the J1850 bus. See
symbol invalid or out of range flag in the BDLC_DLCBSVR register is set when a symbol error is
detected. If the interrupt enable bit (IE in the BDLC_DLCBCR1 register) is set, an interrupt request from
the BDLC module is generated. Reading the BDLC_DLCBSVR register clears this flag.
6.4.2.11.4
A framing error is detected when a received symbol occurs in an inappropriate location in the message
frame. The following situations result in framing errors:
The symbol invalid or out of range flag in the BDLC_DLCBSVR register is set when a framing error is
detected. If the interrupt enable bit (IE in the BDLC_DLCBCR1 register) is set, an interrupt request from
the BDLC module is generated. Reading the BDLC_DLCBSVR register clears this flag.
6.4.2.11.5
If the bus is shorted to V
to transmit a message. As long as the short remains, the BDLC never attempts to transmit a message onto
the J1850 bus.
If the bus is shorted to ground, the BDLC module sees an idle bus, begin to transmit the message, and then
detect a transmission error, since the short to ground would not allow the bus to be driven to the active
(dominant) state. The BDLC module waits for assertion of the receive pin for (64 - analog round trip delay)
t
BDLC module waits for (280 - analog round trip delay) t
round trip delay is determined by the value stored in the BDLC_DLCBARD register. The BDLC module
sets the symbol invalid or out of range flag in the BDLC_DLCBSVR register, aborts that transmission, and
waits for the next CPU command to transmit. In this case, the transmitter does not have to wait for an EOF
symbol to be received to be enabled. If the interrupt enable bit (IE in the BDLC_DLCBCR1 register) is
set, an interrupt request from the BDLC module is generated. Reading the BDLC_DLCBSVR register
clears this flag.
If the bus fault is temporary, as soon as the fault is cleared, the BDLC module resumes normal operation.
If the bus fault is permanent, it may result in permanent loss of communication on the J1850 bus.
6-32
bdlc
•
•
•
•
cycles, after assertion of the transmit pin, before detecting the error. If the transmission is an IFR, the
An active logic 0 or logic 1 received as the first symbol of the frame.
An SOF symbol received in any location other than the first symbol of a frame. Erroneous locations
include: Within the data portion of a message or IFR; Immediately following the EOD in a message
or IFR.
An EOD symbol received on a non-byte boundary in a message or IFR.
An active logic 0 or logic 1 received immediately following the EOD at the end of an IFR.
If a bus fault occurs, the response of the BDLC module depends upon the type of bus fault.
Symbol Error
Framing Error
Bus Fault
DD
Invalid Passive Bit
, the BDLC module waits for the bus to fall to a passive state before it attempts
MPC5125 Microcontroller Reference Manual, Rev. 2
and
Invalid Active
bdlc
cycles before detecting an error. The analog
Bit, which define invalid symbols. The
Freescale Semiconductor