MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 627

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

When entering the power down mode, the MSCAN immediately stops all ongoing transmissions and
receptions, potentially causing CAN protocol violations. To protect the CAN bus system from fatal
consequences of violations to the above rule, the MSCAN immediately drives the TXCAN pin into a
recessive state.
In power down mode, all clocks are stopped and no registers can be accessed. If the MSCAN was not in
sleep mode before power down mode became active, the module would perform an internal recovery cycle
after powering up. This causes some fixed delay before the module enters run mode again.
22.4.8.4
The MSCAN can be programmed to wake-up the MSCAN as soon as bus activity is detected (see control
bit WUPE in
22.4.9
The reset state of each individual bit is listed in
the registers and their bit-fields.
22.4.10 Interrupts
This section describes all interrupts originated by the MSCAN. It documents the enable bits and generated
flags. Each interrupt is listed and described separately.
22.4.11 Description of Interrupt Operation
The MSCAN supports one interrupt vector mapped onto eight different interrupt sources, any of which can
be individually masked (for details, see sections
Register (CANRIER),”
(CANTIER)”).
Freescale Semiconductor
Reset Initialization
Wake-Up Interrupt (WUPIF)
Error Interrupts Interrupt (CSCIF, OVRIF)
Programmable Wake-Up Function
Section 22.3.2.1, “MSCAN Control 0 Register
You are responsible for ensuring that the MSCAN is not active when Power
Architecture deep sleep mode is entered. The recommended procedure is to
bring the MSCAN into Sleep mode before the Power Architecture enters
deep sleep mode. Otherwise, the abort of an ongoing message can cause an
error condition and impact other CAN bus devices.
The dedicated interrupt vector addresses are defined in
“Integrated Programmable Interrupt Controller (IPIC).”
to
Interrupt Source
Section 22.3.2.8, “MSCAN Transmitter Interrupt Enable Register
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 22-34. Interrupt Vectors
Section 22.3.2, “Register Descriptions,”
Section 22.3.2.6, “MSCAN Receiver Interrupt Enable
NOTE
NOTE
CCR Mask
I bit
I bit
(CANCTL0)”).
CANRIER (WUPIE)
CANRIER (CSCIE, OVRIE)
Chapter 18,
Local Enable
which details all
MSCAN
22-49