MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 646

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

NAND Flash Controller (NFC)
23-16
ECC_SRAM_ADDR[11:3]
CMD_TIMEOUT[4:0]
STOP_ON_WERR
ECC_SRAM_REQ
ECC_MODE[2:0]
ID_COUNT[2:0]
FAST_FLASH
DMA_REQ
16BIT
Field
Stop on Write Error.
0 No stop on write error.
1 Auto sequencer (see
Byte address in SRAM where ECC status is written.
0 Do not write ECC status to SRAM.
1 Write ECC status to SRAM.
0 Do not transfer sector after ECC done.
1 After ECC done, transfer sector using DMA.
ECC mode.
000 No correction, ECC bypass.
001 4-error correction (8 ECC bytes).
010 6-error correction (12 ECC bytes).
011 8-error correction (15 ECC bytes).
100 12-error correction (23 ECC bytes).
101 16-error correction (30 ECC bytes).
110 24-error correction (45 ECC bytes).
111 32-error correction (60 ECC bytes).
0 Slow flash timing. Clock in read data on rising edge of read strobe.
1 Fast flash timing. Clock in read data 1/2 clock later than rising edge of read strobe
See
Number of bytes that will be read for the read id command.
The number of flash_clk cycles from NFC_WE high to NAND flash busy (t
high to NFC_RE low (tWHR).
After last command is issued to flash, before sample NFC_R/B, NFC must wait for t
t
is idle. NFC can issue new commands to the flash. If NFC_R/B is sampled low, the NAND flash
is busy.
When reading status or ID from the NAND flash, after the last command is issued to the flash,
the NFC must wait for t
Note: t
0 8-bit wide flash mode.
1 16-bit wide flash mode.
WB
Table 23-16. FLASH_CONFIG field descriptions
MPC5125 Microcontroller Reference Manual, Rev. 2
, if NFC_R/B is sampled high, NFC considers the command to be timed out, and the flash
Section 23.8.4, “Fast Flash Configuration for EDO,”
details of t
WB
exists in page program/read, block erase,etc. Refer to the NAND flash datasheet for
WB
and t
WHR
Table
WHR
, then assert NFC_RE low, to read out valid status or ID.
.
23-22) will stop on write error.
Description
for more information.
Freescale Semiconductor
WB
), or from NFC_WE
WB
. After