MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 803

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

28.4.5
SDHC uses the DAT3 pin to detect card insertion or removal. To use this feature of the SDHC, chip level
integration needs to pull-down this pad as a default state. When no card exists on the MMC/SD bus, DAT3
defaults to a low voltage level. When any card is inserted to or removed from the socket, SDHC detects
the logic value changes on the DAT3 pin and generates an interrupt.
Because the mechanism is based on the value of the DAT3 line, only single-card systems can benefit from
card detection. To avoid conflicts of card insertion/removal detection and the data value changes on DAT3
due to data transfer, disable the card insertion interrupt when a card is detected in the socket and enabled
when the card is removed from the socket. The card removal interrupt can only be enabled when no bus
activity occurs on DAT3.
To avoid false status bit generation during data transfer, the card insertion/removal is masked by
corresponding interrupt enable bits in the SDHC_INT_CNTR register.
Above all, there are three interrupt sources: card removal interrupt, card insertion interrupt, and SDIO card
interrupt. All interrupt sources are ORed between the peripheral and the interrupt controller.
Freescale Semiconductor
Clear IRQ0
Figure 28-21. A) Card Interrupt Scheme; B) Card Interrupt Detection and Handling Procedure
Card Insertion and Removal Detection
SDIO Card
SD Host
IRQ0
SDIO IRQ Enable
SDIO IRQ Status
SDHC Registers
Function 0
IP Bus
IRQ Detecting & Steering
IRQ Routing
SDIO Card
MPC5125 Microcontroller Reference Manual, Rev. 2
A)
IRQ to CPU
Function 1
Command/
Response
Handling
IRQ1
Clear IRQ1
Interrogate and service Card IRQ
Detect and steer card IRQ
Read IRQ Status Register
Disable Card IRQ in Host
Enable card IRQ in Host
Enable card IRQ in Host
Clear Card IRQ in Card
Secure Digital Host Controller (SDHC)
Response Error?
Start
End
B)
No
Yes
28-31