MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 472

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Integrated Programmable Interrupt Controller (IPIC)
18.2.1.12 System Mixed Interrupt Group B Priority Register (IPIC_SMPRR_B)
The System Mixed Interrupt Group B Priority Register (IPIC_SMPRR_B), shown in
the priority between PSC0, PSC1, PSC2, and PSC3.
18-24
Address: Base + 0x34
Reset
Reset
MIXA1P–
MIXA0P
MIXA7P
Field
W
W
R
R
16
0
1
0
Figure 18-15. System Mixed Interrupt Group B Priority Register (IPIC_SMPRR_B)
MIXB0P
MIXA4P
MIXA0 Priority order. Defines which interrupt source asserts its request in the MIXA0 priority position. The
user should not program the same code to more than one priority position (0–7). These bits can be changed
dynamically. The definition of MIXA0P is as follows:
000 DIU asserts its request to the MIXA0 position.
001 DMA2 asserts its request to the MIXA0 position.
010 Reserved.
011 Reserved.
100 IRQ0 asserts its request to the MIXA0 position. This field for MIXA0 position is valid (must not be
101 IRQ1 asserts its request to the MIXA0 position.
110 Reserved.
111 Reserved.
Same as MIXA0P, but for MIXA1P–MIXA7P.
17
0
0
1
ignored) if IRQ0 signal configured as an external maskable interrupt (IPIC_SEMSR[SIRQ0] = 0).
18
0
0
2
19
0
1
3
Table 18-15. IPIC_SMPRR_A field descriptions
MPC5125 Microcontroller Reference Manual, Rev. 2
MIXB1P
MIXA5P
20
4
0
0
21
1
1
5
22
0
1
6
MIXB2P
MIXA6P
23
1
1
7
Description
24
8
0
0
25
9
0
1
MIXB3P
MIXA7P
10
26
1
1
11
27
1
1
12
28
Figure
0
0
0
0
Freescale Semiconductor
Access: User read/write
13
29
0
0
0
0
18-15, defines
14
30
0
0
0
0
15
31
0
0
0
0