MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 551

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

21.2.1.1.6
Freescale Semiconductor
Address: Base + 0x02C
Reset
Reset
BWE[6:0]
BRE[6:0]
SLB[6:0]
CW[6:0]
DC[6:0]
Field
Field
DC7
W
W
R
R
16
0
0
0
0
0
Chip Select Deadcycle Control (LPC_CSDC) Register
Same as CW7, but for CS6–CS0/Boot.
Same as SLB7, but for CS6–CS0/Boot.
Same as BWE7, but for CS6–CS0/Boot.
Same as BRE7, but for CS6–CS0/Boot.
Deadcycles can be specified as 0 to 3. Deadcycles are added to the end of a Chip Select 7 read access and
occur in addition to any cycles that may already exist. These cycles provide the device additional time to
tri-state its bus after a read operation.
00 Device can drive data one LPC clock cycle after CS deassertion.
01 Device can drive data two LPC clock cycle after CS deassertion.
10 Device can drive data three LPC clock cycle after CS deassertion.
11 Device can drive data four LPC clock cycle after CS deassertion.
Same as DC7, but for CS6–CS0/Boot.
17
0
0
0
0
1
Figure 21-7. Chip Select Deadcycle Control (LPC_CSDC) Register
18
1
1
2
DC7
DC3
Table 21-7. LPC_CSBC field descriptions (continued)
19
1
1
3
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 21-8. LPC_CSDC field descriptions
20
4
0
0
0
0
21
0
0
0
0
5
22
1
1
6
DC6
DC2
23
1
1
7
Description
Description
24
8
0
0
0
0
25
9
0
0
0
0
10
26
1
1
DC5
DC1
11
27
1
1
LocalPlus Bus Controller (LPC)
12
28
0
0
0
0
Access: User read/write
13
29
0
0
0
0
14
30
1
1
DC4
DC0
21-11
15
31
1
1