MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 897

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

32.5.5.2
The second doubleword of a queue element transfer descriptor supports hardware-only advance of the data
stream to the next client buffer on short packet. To be more explicit, the host controller always uses this
pointer when the current qTD is retired due to short packet.
32.5.5.3
The third doubleword of a queue element transfer descriptor contains most of the information the host
controller requires to execute a USB transaction (the remaining endpoint-addressing information is
specified in the queue head). Some of the field descriptions in
queue head. See
Freescale Semiconductor
Alternate Next
Total Bytes to
qTD Pointer
Data Toggle
Transfer
C_Page
30:16
14:12
31:5
IOC
Bit
4:1
Bit
31
15
0
T
Alternate Next qTD Pointer
qTD Token
This is the data toggle sequence bit. The use of this bit depends on the setting of the data toggle control bit in
the queue head.
Total Bytes to Transfer. This field specifies the total number of bytes to be moved with this transfer descriptor.
This field is decremented by the number of bytes actually moved during the transaction on the successful
completion of the transaction. The maximum value software may store in this field is 5
the maximum number of bytes five page pointers can access. If the value of this field is 0 when the host
controller fetches this transfer descriptor (and the active bit is set), the host controller executes a zero-length
transaction and retires the transfer descriptor. It is not a requirement for OUT transfers that total bytes to
transfer be an even multiple of QH [Maximum Packet Length]. If software builds such a transfer descriptor for
an OUT transfer, the last transaction is always less than QH [Maximum Packet Length]. Although it is possible
to create a transfer as large as 20 KB, this assumes the page is zero. When the offset cannot be
predetermined, crossing past the fifth page can be guaranteed by limiting the total bytes to 16 KB. Therefore,
the maximum recommended transfer is 16 KB (0x4000).
Interrupt On Complete. If this bit is set, it specifies that when this qTD is completed, the host controller should
issue an interrupt at the next interrupt threshold.
Current Page. This field is used as an index into the qTD buffer pointer list. Valid values are in the range 0x0 to
0x4. The host controller is not required to write this field back when the qTD is retired.
This field contains the physical memory address of the next qTD to be processed in the event that the current
qTD execution encounters a short packet (for an IN transaction). The field corresponds to memory address
signals [31:5], respectively.
Reserved. These bits are reserved and their value has no effect on operation.
Terminate. This bit indicates to the Host Controller that there are no more valid entries in the queue.
0 Pointer is valid (points to a valid Transfer Element Descriptor).
1 Pointer is invalid.
Table 32-58. qTD Alternate Next Element Transfer Pointer (Doubleword 1)
Section 32.5.6, “Queue Head,”
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 32-59. qTD Token (doubleword 2)
for more information on these fields.
Description
Description
Table 32-59
Universal Serial Bus Interface with On-The-Go
reference fields defined in the
×
4K (0x5000). This is
32-69