MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 779

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Freescale Semiconductor
BUF_UND_RUN Buffer Underrun. When set, this bit indicates both X and Y data buffers are empty during a write transfer. In
WRITE_OP_
XBUF_FULL
END_CMD_
BUF_OVFL
SDIO_INT_
ACTIVE
DONE
RESP
Field
X Data Buffer Full. When set, this bit indicates the X data buffer is full during a read transfer. This bit is
automatically cleared when the last byte of data is read out from the FIFO. Refer to
Buffers,”
0
1
this case, the MMC_SD_CLK card clock is stopped automatically by hardware to wait for the DMA or CPU to
put data into the buffers. An interrupt is triggered if the corresponding interrupt control bit is enabled.
0 No buffer underrun.
1 Buffer underrun during a write operation.
Buffer Overflow. When set, this bit indicates both data buffers are full during a read operation. In this case, the
MMC_SD_CLK card clock is stopped automatically by hardware to wait for the DMA or CPU to remove data
out of one of the buffers. An interrupt is triggered if the corresponding interrupt control bit is enabled. Excess
data is ignored by the SDHC.
0 No buffer overflow.
1 Buffer overflow during a read operation.
SDIO Interrupt Active. This bit indicates whether an interrupt from the SDIO card has been detected. When
this bit is set, the SDHC generates an interrupt request if the SDIO interrupt is enabled. Software should clear
the status bit to clear the interrupt request. However, a separate acknowledge command to the card may be
required to clear the source of the SDIO interrupt. Writing a 1 to this bit clears it.
0 No interrupt detected.
1 Interrupt detected using SDIO card bus.
End Command Response. This bit indicates whether a command was successfully transmitted to the card and
the corresponding response was stored in the Response FIFO. This occurs after each command operation.
When this bit is set, the SDHC generates an interrupt request if END_CMD_RESP interrupt is enabled .
Software needs to clear this bit to clear the interrupt request. Writing a 1 to this bit clears it.
0 Command not successful, incomplete. or not applicable (no response).
1 Command transmitted successfully (response received).
Note: When this bit is set, check the response stored in the response FIFO completed without fail. Also, check
Write Operation Done. This indicates a write operation has completed. The flash card might need extra idle
time for write accesses, which requires the SDHC module to wait until the card writes the buffered data to the
inner flash memory. The WRITE_OP_DONE flag indicates the end of the write operation. When this bit is set,
the pre-defined data bytes are written to the card. Software needs to send a STOP command to the card if the
write command is a MMC/SD card write multi-block command. When this bit is set, SDHC generates an
interrupt request if the WRITE_OP_DONE interrupt enable is enabled in the SCDH_INT_CNTR register.
Software needs to clear this bit to clear the interrupt. This is accomplished by writing 1 to this bit.
0
1
Note: When this bit is set, software also needs to check if the write operation completed without a cyclic
X buffer is not full.
X buffer is full.
Write operation in progress or incomplete.
Write operation complete.
the RESP_CRC_ERR (Status[5]) and TIME_OUT_RESP(STATUS[1]) bits to determine if an error
occurred.
redundancy check (CRC) error. Also, software needs to check the
SDHC_STATUS[WR_CRC_ERR_CODE] bitfield and the SDHC_STATUS[WRITE_CRC_ERR] bit to
determine if an error has occurred.
for more information about the data buffers.
Table 28-5. SDHC_STATUS field descriptions (continued)
MPC5125 Microcontroller Reference Manual, Rev. 2
Description
Secure Digital Host Controller (SDHC)
Section 28.4.1, “Data
28-7