MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 132

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Clocks and Low-Power Modes
5.3.1.25
The Out Clock 2 clock config register is shown in
OUT2CCR.
5-32
OUT1_CLK_SR
Address: Base + 0x78
OUT1_DIV
OUT2_DIV
OUT1_EN
OUT2_EN
Reset
Reset
Field
Field
W
W
C
R
R OUT2_CLK_
16
1
0
0
SRC
Out Clock 2 Config Register (OUT2CCR)
OUT1 divider Ratio
A value of 0x0 will bypass the divider.
Note: This value can only be changed when the value of OUT1_EN equals 0.
OUT1 Divider Enable
0 OUT1 divider is disabled.
1 OUT1 divider is enabled.
Out Clock 1 Clock Source.
00 From SYS_CLK.
01 From REF_CLK.
10 From PSC_MCLK_IN.
11 From CAN_CLK_IN.
OUT2 divider Ratio
A value of 0x0 will bypass the divider
Note: This value can only be changed when the value of OUT2_EN equals 0
OUT2 Divider Enable
0 OUT2 divider is disabled
1 OUT2 divider is enabled
17
1
0
1
f
f
out1_clk
out2_clk
18
1
0
0
2
Figure 5-30. Out Clock 2 Clock Config Register (OUT2CCR)
= f
= f
out1_clk_src
out2_clk_src
19
1
0
0
3
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 5-30. OUT2CCR field descriptions
Table 5-29. OUT1CC field descriptions
20
4
1
0
0
/ (OUT1_DIV + 1)
/ (OUT2_DIV + 1)
21
1
0
0
5
22
1
0
0
6
OUT2_DIV
Figure
23
1
0
0
7
Description
Description
5-30.
24
8
1
0
0
Table 5-30
25
9
1
0
0
10
26
1
0
0
defines the bit fields of
11
27
1
0
0
12
28
1
0
0
Freescale Semiconductor
Access: User read/write
13
29
1
0
0
14
30
1
0
0
OUT2
_EN
15
31
0
0
0