MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 44

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

System Configuration and Memory Map (XLBMEN + Mem Map)
2.2.5.1.5
Figure 2-4
2-10
Address: Base + 0x0024 (LPCS0AW)
Address: Base + 0x00A0
START_ADDR Any access on an address between Start and Stop Address enables the corresponding chip select. The
STOP_ADDR
BASE_ADDR
Reset
Reset
Reset
Reset
Field
Field
W
W
W
W
R
R
R
R
Base + 0x0028 (LPCS1AW)
Base + 0x002C (LPCS2AW)
Base + 0x0030 (LPCS3AW)
16
16
0
0
0
shows the DDR Local Access Window Base Address Register (DDRLAWBAR).
0
Figure 2-4. DDR Local Access Window Base Address Register (DDRLAWBAR)
BASE_ADDR
DDR Local Access Window Base Address Register (DDRLAWBAR)
START_ADDR is for the address comparison extended with 0x0000. The STOP_ADDR is for the address
comparison extended with 0xFFFF. This means the minimum address size is 64 k. If the START_ADDR and
STOP_ADDR are set to 0xA000, the access window goes from 0xA000_0000 to 0xA000_FFFF.
Note: CS Boot and CS0 have the same physical CS pin.
Identifies the 20 most-significant address bits of the base address of local access window n. The specified
base address should be aligned to the window size, as defined by DDRLAWAR[SIZE].
17
17
0
0
1
1
Figure 2-3. LocalPlus CS0–7 Access Window Registers (LPCSxAW)
18
18
0
0
2
2
19
19
1
0
3
3
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 2-8. DDRLAWBAR0 field descriptions
Table 2-7. LPCSxAW field descriptions
20
20
4
4
0
0
0
Base + 0x0034 (LPCS4AW)
Base + 0x0038 (LPCS5AW)
Base + 0x003C (LPCS6AW)
Base + 0x0040 (LPCS7AW)
21
21
0
0
0
5
5
22
22
0
0
0
6
6
START_ADDR
See
STOP_ADDR
See
BASE_ADDR
23
23
0
0
0
7
7
Description
Description
Table 2-6
Table 2-6
24
24
8
8
0
0
0
25
25
9
9
0
0
0
10
26
10
26
0
0
0
11
27
11
27
0
0
0
12
28
12
28
0
0
0
Freescale Semiconductor
Access: User read/write
Access: User read/write
13
29
13
29
0
0
0
14
30
14
30
0
0
0
15
31
15
31
0
0
0