MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 962

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Universal Serial Bus Interface with On-The-Go
denote the state of the Active bit in the Status field of an siTD. The Bold, dotted arcs denote the transitions
between these states. Solid circles denote the states of the split transaction state machine and the solid arcs
denote the transitions between these states. Dotted arcs and boxes reference actions that take place either
as a result of a transition or from being in a state.
Periodic Isochronous—Do-Start-Split
Isochronous split transaction OUTs use only this state. An siTD for a split-transaction isochronous IN is
initialized to this state, the siTD transitions to this state from Do Complete Split when a case 2a (IN), or
2b scheduling boundary isochronous split-transaction completes.
Each time the host controller reaches an active siTD in this state, it checks the siTD [S-mask] against
cMicroFrameBit. If there is a one in the appropriate position, the siTD executes a start-split transaction.
By definition, the host controller cannot reach an siTD at the wrong time. If the I/O field indicates an IN,
the start-split transaction includes only the extended token plus the full-speed token. Software must
initialize the siTD [Total Bytes To Transfer] field to the number of bytes expected. This is usually the
maximum packet size for the full-speed endpoint. The host controller exits this state when the start-split
transaction is complete.
The remainder of this section is specific to an isochronous OUT endpoint (the I/O field indicates an OUT).
When the host controller executes a start-split transaction for an isochronous OUT it includes a data
payload in the start-split transaction. The memory buffer address for the data payload is constructed by
concatenating siTD [Current Offset] with the page pointer indicated by the page select field (siTD [P]). A
32-134
Active = 0
Transaction
Complete
IN Split
Transaction
OUT Split
Complete
Figure 32-70. Split Transaction State Machine for Isochronous
Advance Data
Buffer State
Active
Not
Active = 0
MPC5125 Microcontroller Reference Manual, Rev. 2
Case 2(a,b)
Complete
siTD x–1
MDATA
Active = 1
Complete-
Active
Start-
Split
Split
Do
Do
siTD.S-Mask & cMicroFrameBit
Direction .eq. OUT
Not Last
NYET
CheckPreviousBit(C-prog-mask,
.and.
.and.
C-Mask, cMicroFrameBit)
Issue Start-Split
Transaction
Issue Complete-Split
siTD.S-Mask & cMicroFrameBit
Transaction
Direction .eq. IN
.and.
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