MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 850

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Universal Serial Bus Interface with On-The-Go
32.2.4.3
32-22
ULPII
Field
NAKI
HCH
RCL
UPI
UAI
TI1
TI0
AS
PS
USB Interrupt Enable Register (USB_USBINTR)
General Purpose Timer Interrupt 1 (GPTINT1). This bit is set when the counter in the USB_GPTIMER1CTRL
register transitions to 0. Writing a 1 to this bit clears it.
General Purpose Timer Interrupt 0 (GPTINT0). This bit is set when the counter in the USB_GPTIMER0CTRL
register transitions to 0. Writing a 1 to this bit clears it.
USB Host Periodic Interrupt (USBHSTPERINT). This bit is set by the host controller when the cause of an
interrupt is a completion of a USB transaction where the transfer descriptor (TD) has an interrupt on complete
(IOC) bit set and the TD was from the periodic schedule.
This bit is also set by the host controller when a short packet is detected and the packet is on the periodic
schedule. A short packet is when the actual number of bytes received was less than the expected number of
bytes.
This bit is not used by the device controller and is always 0.
USB Host Asynchronous Interrupt (USBHSTASYNCINT). This bit is set by the host controller when the cause
of an interrupt is a completion of a USB transaction where the transfer descriptor (TD) has an interrupt on
complete (IOC) bit set and the TD was from the asynchronous schedule.
This bit is also set by the Host when a short packet is detected and the packet is on the asynchronous
schedule. A short packet is when the actual number of bytes received was less than the expected number of
bytes.
The device controller does not use this bit and it is always 0.
NAK Interrupt Bit. This bit is read-only. It is set by hardware when for a particular endpoint both the TX/RX
endpoint NAK bit and the corresponding TX/RX endpoint NAK enable bit are set. This bit is automatically
cleared by hardware when the all the enabled TX/RX endpoint NAK bits are cleared.
Asynchronous Schedule Status. This bit reports the current real status of the asynchronous schedule. The
controller is not required to immediately disable or enable the asynchronous schedule when software
transitions the asynchronous schedule enable bit in the USB_USBCMD register. When this bit and the
asynchronous schedule enable bit are the same value, the asynchronous schedule is enabled (1) or disabled
(0). Used only in host mode.
0 Disabled.
1 Enabled.
Periodic Schedule Status. This bit reports the current real status of the periodic schedule. The controller is not
required to immediately disable or enable the periodic schedule when software transitions the periodic
schedule enable bit in the USB_USBCMD register. When this bit and the periodic schedule enable bit are the
same value, the periodic schedule is enabled (1) or disabled (0). Used only in host mode.
0 Disabled.
1 Enabled.
Reclamation. This is a status bit that detects an empty asynchronous schedule. Used only by the host mode.
0 Non-empty asynchronous schedule.
1 Empty asynchronous schedule.
Host Controller HaIted. This bit is 0 when the run/stop bit is a 1. The controller sets this bit to 1 after it has
stopped executing because of the run/stop bit being set to 0, by software or the host controller hardware (e.g.,
internal error). Used only in host mode.
0 Running.
1 Halted.
ULPI Interrupt. When the ULPI Viewport is present in the design, an event completion sets this interrupt.
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 32-17. USB_USBSTS field descriptions
Description
Freescale Semiconductor