MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 491

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

18.3.7
By programming the system interrupt mask registers, IPIC_SIMSRx and IPIC_SEMSR, the user can mask
interrupt requests to the core. Each IPIC_SIMSRx and IPIC_SEMSR bit corresponds to an interrupt
source. To enable an interrupt, set the corresponding IPIC_SIMSR or IPIC_SEMSR bit. When a masked
interrupt source has a pending interrupt request, the corresponding IPIC_SIPNRx or IPIC_SEMSR bit is
set, even though the interrupt is not generated to the core. The user can mask all interrupt sources to
implement a polling interrupt servicing scheme.
When an interrupt source has multiple interrupting events, the user can individually mask these events by
programming a mask register within that particular block.
multiple interrupting events.
an example.
Freescale Semiconductor
Masking Interrupt Sources
Priority Level
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
Table 18-28. Interrupt Source Priority Levels (continued)
Figure 18-29
MPC5125 Microcontroller Reference Manual, Rev. 2
Interrupt Source Description
SYSC5 (Spread)
SYSD5 (Spread)
SYSB6 (Spread)
SYSA6 (Spread)
SYSC6 (Spread)
SYSD6 (Spread)
SYSB7 (Spread)
SYSA7 (Spread)
SYSC7 (Spread)
SYSD7 (Spread)
MIXB7 (Spread)
shows an example of how the masking occurs, using a DDR as
PRIOMON
Reserved
Reserved
Reserved
MSCAN3
MSCAN4
GPT12
GPT13
GPT14
GPT15
IIM
Table 18-28
Integrated Programmable Interrupt Controller (IPIC)
Yes (No for ext. interrupts)
shows which interrupt sources have
Multiple Events
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
18-43