MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 948

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Universal Serial Bus Interface with On-The-Go
it encounters the restore FSTN, (Restore-N), during micro-frames 0 and 1, it uses Restore-N. Normal path
link pointer to traverse to the next data structure (normal schedule traversal). This is because the host
controller must use a restore FSTN's normal path link pointer when not executing in a recovery-path mode.
The nodes traversed during frame N include: {8
In frame N+1 (micro-frames 0 and 1), when the host controller encounters save-path FSTN (Save-N), it
observes that Save-N.Back Path Link Pointer.T-bit is zero (definition of a Save-Path indicator). The host
controller saves the value of Save-N. Normal path link pointer and follows Save-N.Back Path Link Pointer.
At the same time, it sets an internal flag indicating that it is now in recovery path mode (the recovery path
is annotated in
structures on the recovery path and executing only those bus transactions as noted above, on the recovery
path until it reaches restore FSTN (Restore-N). Restore-N.Back Path Link Pointer.T-bit is set (definition
of a Restore indicator), so the host controller exits recovery path mode by clearing the internal recovery
path mode flag and commences (restores) schedule traversal using the saved value of the save-place
FSTN’s normal path link pointer (for example, Save-N.Normal Path Link Pointer). The nodes traversed
during these micro-frames include: {8
10...}.
In frame N+1 (micro-frames 2-7), when the host controller encounters save-path FSTN Save-N, it
unconditionally follows Save-N.Normal Path Link Pointer. The nodes traversed during these micro-frames
include: {8
Software Operational Model for FSTNs
Software must create a consistent, coherent schedule for the host controller to traverse. When using
FSTNs, system software must adhere to the following rules:
32-120
•
•
•
•
Each save-place indicator requires a matching restore indicator.
The save-place indicator is an FSTN with a valid back path link pointer and T-bit equal to zero.
The Back path link pointer [Typ] field must be set to indicate the referenced data structure is a
queue head. The restore indicator is an FSTN with its back path link pointer [T] bit set.
A restore FSTN may be matched to one or more save-place FSTNs. For example, if the schedule
includes a poll-rate 1 level, system software only needs to place a restore FSTN at the beginning
of this list to match all possible save-place FSTNs.
If the schedule does not have elements linked at a poll-rate level of one, and one or more save-place
FSTNs are used, system software must ensure the restore FSTN's normal path link pointer's T-bit
is set, as this marks the end of the periodic list.
When the schedule does have elements linked at a poll rate level of one, a restore FSTN must be
the first data structure on the poll rate one list. All traversal paths from the frame list converge on
the poll-rate one list. System software must ensure that recovery path mode is exited before the host
controller is allowed to traverse the poll rate level one list.
A save-place FSTN's back path link pointer must reference a queue head data structure. The
referenced queue head must be reachable from the previous frame list location. In other words, if
the save-place FSTN is reachable from frame list offset N, then the FSTN's back path link pointer
must reference a queue head that is reachable from frame list offset N-1.
3.0
, 8
Figure 32-66
3.1
, 8
3.2
, Save-A, 4
with a large dashed line). The host controller continues traversing data
MPC5125 Microcontroller Reference Manual, Rev. 2
3
, 2
3.0
1
, Restore-N, 1
, 8
3.1
, 8
3.2
2.0
, Save-A, 8
, 8
2.1
0
...}.
, 8
2.2
, 8
2.2
2.3
, 8
, 4
2.3
2
, 4
, 2
2
, 2
0
, Restore-N, 1
0
, Restore-N, 4
Freescale Semiconductor
0
...}.
3
, 2
1
, Restore-N,