MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 498

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Inter-Integrated Circuit (I
19.1.5.2
I
synchronization procedure determines the bus clock.
Because wire-AND logic is used on the SCL line, a high-to-low transition on the SCL line affects all
devices connected on the bus. The devices start counting their low period. After a device clock goes low,
it holds the SCL line low until the clock high state is reached. However, the change of low-to-high in this
device clock may not change the SCL line state if another device clock remains within its low period.
Therefore, the synchronized clock SCL is held low by the device with the longest low period. Devices with
shorter low periods enter a high wait state during this time. See
When all devices concerned have counted off their low period, the synchronized clock SCL line is released
and pulled high. No difference exists between device clocks and the SCL line state. All devices start
counting their high periods. The first device to complete its high period pulls the SCL line low again.
19-6
2
C is a true multi-master bus. If two or more masters try to control the bus at the same time, a clock
•
•
The master reading a slave immediately after first byte. At the moment of the first acknowledge,
the master-transmitter becomes a master-receiver and the slave-receiver becomes a
slave-transmitter.
The START condition and slave address both repeated using the repeated START signal. This
communicates with the same slave in a different mode without releasing the bus. The master
transmits data to the slave first, and then the master reads data from the slave by reversing the R/
bit.
ST
Slave Address
Clock Synchronization
7-Bit
ST
ST
2
C)
7-Bit Slave Address
7-Bit Slave Address
R/W
1
ST = Start
SP = Stop
A = Acknowledge (SDA low)
A = Not Acknowledge (SDA high)
Rept ST = Repeated Start
A
MPC5125 Microcontroller Reference Manual, Rev. 2
Figure 19-5. Data Transfer, Combined Format
DATA
R/W
R/W
0
1
A/A
A
A
Rept
ST
Register Address
Slave Address
DATA
7-Bit
From Master to Slave
From Slave to Master
A
A
R/W
Figure
0
A
DATA
DATA
19-6.
DATA
A/A
A
SP
SP
A
Freescale Semiconductor
DATA A/A SP
W