MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 935

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

With the exception of a NAK response (when RL field is zero), the host controller always writes the results
of the transaction back to the overlay area in main memory. This includes when the transfer completes. For
a high-speed endpoint, the queue head information written back includes minimally the following fields:
For a low- or full-speed device the queue head information written back also includes the fields:
The duration of this state depends on the time it takes to complete the transaction(s) and the status write to
the overlay is committed.
32.6.9.3.1
A halted endpoint is defined only for the transfer types that are managed via queue heads (control, bulk
and interrupt). The following events indicate that the endpoint has reached a condition where no more
activity can occur without intervention from the driver:
When any of these events occur (for a queue head) the Host Controller halts the queue head and set the
USBERRINT status bit in the USB_USBSTS register to a one. To halt the queue head, the Active bit is set
to a zero and the Halted bit is set to a one. There may be other error status bits that are set when a queue
is halted. The host controller always writes back the overlay area to the source qTD when the transfer is
complete, regardless of the reason (normal completion, short packet or halt). The host controller does not
advance the transfer state on a transaction that results in a Halt condition (i.e., no updates necessary for
Total Bytes to Transfer, C_Page, Current Offset, and dt). The host controller must update CErr as
appropriate. When a queue head is halted, the USB Error Interrupt bit in the USB_USBSTS register is set
to a one. If the USB Error Interrupt Enable bit in the USB_USBINTR register is set to a one, a hardware
interrupt is generated at the next interrupt threshold.
32.6.9.3.2
Asynchronous Schedule Park mode is a special execution mode that can be enabled by system software,
where the host controller is permitted to execute more than one bus transaction from a high-speed queue
head in the Asynchronous schedule before continuing horizontal traversal of the Asynchronous schedule.
This feature has no effect on queue heads or other data structures in the Periodic schedule. This feature is
similar in intent to the Mult feature that is used in the Periodic schedule. Whereas the Mult feature is a
Freescale Semiconductor
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The PID code is an IN, and the number of bytes moved during the transaction is less than the
Maximum Packet Length. When this occurs, the Active bit is set to zero and a short packet
condition exists. The short-packet condition is detected during the Advance Queue state. Refer to
Section 5.12 for additional rules for managing low- and full-speed transactions.
The PID Code field indicates an IN and the device sends more than the expected number of bytes
(e.g., Maximum Packet Length or Total Bytes to Transfer bytes, whichever is less) (i.e., a packet
babble). This results in the host controller setting the Halted bit to a one.
NakCnt, dt, Total Bytes to Transfer, C_Page, Status, CERR, and Current Offset
C-prog-mask, FrameTag and S-bytes.
An endpoint may return a STALL handshake during a transaction,
A transaction had three consecutive error conditions, or
A Packet Babble error occurs on the endpoint.
Halting a Queue Head
Asynchronous Schedule Park Mode
MPC5125 Microcontroller Reference Manual, Rev. 2
Universal Serial Bus Interface with On-The-Go
32-107