MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 1031

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Freescale Semiconductor
from Module Base
Address Offset
0x08C–0x0C3
0x0C8–0x0E3
0x028–0x03C
0x018–0x023
0x048–0x063
0x068–0x083
0x0F0–0x117
0x128–0x143
0x154–0x17F
0x0EC
0x0C4
0x0E4
0x0E8
0x11C
0x14C
0x010
0x014
0x024
0x040
0x044
0x064
0x084
0x088
0x118
0x120
0x124
0x144
0x148
0x150
0x180
MPC5125 Microcontroller Reference Manual, Rev. 2, Release Candidate
ETH_R_DES_ACTIVE—CSR Receive Descriptor Active
Register
ETH_X_DES_ACTIVE—CSR Transmit Descriptor Active
Register
Reserved
ETH_ECNTRL—Ethernet Control register
Reserved
ETH_MII_DATA—MII Management Frame Register
ETH_MII_SPEED—MII Speed Control Register
Reserved
ETH_MIB_CONTROL—MIB Control Register
Reserved
ETH_R_CNTRL—Receive Control Register
ETH_R_HASH—Receive Hash Register
Reserved
ETH_X_CNTRL—Transmit Control Register
Reserved
ETH_PADDR1—Physical Address Low Register
ETH_PADDR2—Physical Address High Register
ETH_OP_PAUSE—Opcode/Pause Duration Register
Reserved
ETH_IADDR1—Descriptor Individual Address 1
ETH_IADDR2—Descriptor Individual Address 2
ETH_GADDR1—Descriptor Group Address 1
ETH_GADDR2—Descriptor Group Address 2
Reserved
ETH_X_WMRK—FIFO Transmit FIFO Watermark
Reserved
ETH_R_BOUND—FIFO Receive Bound Register
ETH_R_FSTART—FIFO Receive Start Register
Reserved
ETH_R_DES_START—Beginning of Receive Descriptor
Ring
Table A-2. MPC5125 Detailed Register Map (continued)
Register
Access Reset Value
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
0xC000_0000
0x05EE_0001
0x0001_UUUU
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_8808
0x0000_0000
0x0000_0600
0x0000_0500
—
—
—
—
—
3
3
3
3
3
1
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Section/Page
Memory Map
A-27