MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 594

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

MSCAN
1
22.3.2.6
This register contains the interrupt enable bits for the interrupt flags described in the CANRFLG register.
Read: Anytime
Write: Anytime when out of initialization mode
22-16
Redundant Information for the most critical CAN bus status which is bus-off. This only occurs if the Tx error counter exceeds
a number of 255 errors. Bus-off affects the receiver state. As soon as the transmitter leaves its bus-off state the receiver state
skips to RxOK too. Refer also to TSTAT[1:0] coding in this register.
RSTAT[1:0]
TSTAT[1:0]
OVRIF
RXFIF
Field
MSCAN Receiver Interrupt Enable Register (CANRIER)
WUPIE, CSCIE, OVRIE, and RXFIE are held in the reset state when the
initialization mode is active (INITRQ = 1 and INITAK = 1). This register is
writable when not in initialization mode (INITRQ = 0 and INITAK = 0).
Receiver Status Bits. The values of the error counters control the actual CAN bus status of the MSCAN. As
soon as the status change interrupt flag (CSCIF) is set, these bits indicate the appropriate receiver related
CAN bus status of the MSCAN. The coding for the bits RSTAT1, RSTAT0 is:
00
01
10
11
Transmitter Status Bits. The values of the error counters control the actual CAN bus status of the MSCAN. As
soon as the status change interrupt flag (CSCIF) is set, these bits indicate the appropriate transmitter related
CAN bus status of the MSCAN. The coding for the bits TSTAT1, TSTAT0 is:
00
01
10
11
Overrun Interrupt Flag is set when a data overrun condition occurs. If not masked, an error interrupt is pending
while this flag is set.
0 No data overrun condition.
1 A data overrun detected.
Receive Buffer Full Flag is set by MSCAN when a new message is shifted into the RX FIFO. Flag indicates
whether the shifted buffer is loaded with a correctly received message (matching identifier, matching cyclic
redundancy code (CRC) and no other errors detected). After Power Architecture reads the message from the
RxFG buffer in the Rx FIFO, the RxF flag must be cleared to release the buffer.
A set RxF flag prohibits shifting of the next FIFO entry into the foreground buffer (RxFG). If not masked, an
RX interrupt is pending while this flag is set.
To ensure data integrity, do not read the Rx buffer registers while RXFIF flag is cleared.
0 No new message available within the RxFG.
1 The receiver FIFO is not empty. A new message is available in the RxFG buffer.
RxOK: 0 ≤ receive error counter ≤ 96
RxWRN: 96 < receive error counter ≤ 127
RxERR: 127 < receive error counter
Bus-off
TxOK: 0 ≤ transmit error counter ≤ 96
TxWRN: 96 < transmit error counter ≤ 127
TxERR: 127 < transmit error counter ≤ 255
Bus-Off: transmit error counter > 255
1
Table 22-8. CANRFLG field descriptions (continued)
: transmit error counter > 255
MPC5125 Microcontroller Reference Manual, Rev. 2
NOTE
Description
Freescale Semiconductor