MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 920

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Universal Serial Bus Interface with On-The-Go
The asynchronous schedule status bit in the USB_USBSTS register indicates status of the asynchronous
schedule. System software enables (or disables) the asynchronous schedule by writing a one (or zero) to
the asynchronous schedule enable bit in the USB_USBCMD register. Software can then poll the
asynchronous schedule status bit to determine when the asynchronous schedule has made the desired
transition. Software must not modify the asynchronous schedule enable bit unless the value of the
asynchronous schedule enable bit equals that of the asynchronous schedule status bit.
The asynchronous schedule manages all control and bulk transfers. Control and bulk transfers are managed
using queue head data structures. The asynchronous schedule is based at the USB_ASYNCLISTADDR
register. The default value of the USB_ASYNCLISTADDR register after reset is undefined and the
schedule is disabled when the asynchronous schedule enable bit is cleared.
Software may only write this register with defined results when the schedule is disabled. For example,
asynchronous schedule enable bit in the USB_USBCMD and the asynchronous schedule status bit in the
USB_USBSTS register are cleared. System software enables execution from the asynchronous schedule
by writing a valid memory address (of a queue head) into this register. Then software enables the
asynchronous schedule by setting the asynchronous schedule enable bit is set. The asynchronous schedule
is actually enabled when the asynchronous schedule status bit is set.
When the host controller begins servicing the asynchronous schedule, it begins by using the value of the
USB_ASYNCLISTADDR register. It reads the first referenced data structure and begins executing
transactions and traversing the linked list as appropriate. When the host controller completes processing
the asynchronous schedule, it retains the value of the last accessed queue head's horizontal pointer in the
USB_ASYNCLISTADDR register. Next time the asynchronous schedule is accessed, this is the first data
structure that is serviced. This provides round-robin fairness for processing the asynchronous schedule.
A host controller completes processing the asynchronous schedule when:
The queue heads in the asynchronous list are linked into a simple circular list as shown in
Queue head data structures are the only valid data structures that may be linked into the asynchronous
schedule. An isochronous transfer descriptor (iTD or siTD) in the asynchronous schedule yields undefined
results.
The maximum packet size field in a queue head is sized to accommodate the use of this data structure for
all non-isochronous transfer types. The USB Specification, Revision 2.0 specifies the maximum packet
sizes for all transfer types and transfer speeds. System software should always parameterize the queue head
data structures according to the core specification requirements.
32.6.7.1
This is a software requirement section. There are two independent events for adding queue heads to the
asynchronous schedule. The first is the initial activation of the asynchronous list. The second is inserting
a new queue head into an activated asynchronous list.
32-92
•
•
•
The end of a micro-frame occurs.
The host controller detects an empty list condition
The schedule has been disabled via the Asynchronous Schedule Enable bit in the USB_USBCMD
register.
Adding Queue Heads to Asynchronous Schedule
MPC5125 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor
Figure
32-52.