MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 709

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

25.5
This section describes the different PSC operation modes, including the pin muxing, the module
configuration, signal definition, and some programming examples. All PSCs are independent and can be
used at the same time in different modes.
Freescale Semiconductor
En_OutBuf
UseEOF
EnAC97
MSTR
CPOL
CPHA
Field
SPI
Modes of Operation
Codec. Normal AC97 mode. Takes effect only when the AC97 mode is selected.
(SIM = 0x3)
0 If AC97 mode was selected, Legacy AC97 mode used.
1 If AC97 mode was selected, AC97 mode transmits and receives the data.
Other Modes. Reserved.
Codec. SPI mode.
0 PSC does not behave like an SPI.
1 PSC behaves like an SPI.
Other Modes. Reserved.
Codec. SPI Master mode. Takes effect only when bit SICR[SPI mode] equals 1. Also, the GenClk bit must be
set to enable the clock generation behavior of the SPI master mode.
0 PSC behaves as an SPI slave.
1 PSC behaves as an SPI master.
Other Modes. Reserved.
Codec. SPI Clock Polarity. Takes effect only when bit SICR[SPI mode] equal 1.
This bit selects an inverted or non-inverted SPI clock. To transmit data between SPI modules, the SPI modules
must have identical CPOL values.
0 Active-low clocks selected; SCK idles high.
1 Active-high clocks selected; SCK idles low.
Other Modes. Reserved.
Codec. SPI Clock Phase
This bit is used to shift the SCK serial clock. To transmit data between SPI modules, the SPI modules must
have identical CPHA values.
0 Data transfer starts which assertion of SS.
1 Data transfer starts with the first edge of SCK.
Other modes. Reserved.
Codec. Use End-of-Frame flag takes effect only when bit 16 SPI mode equals 1.
0 One, two, or four bytes are transferred while slave select (SS) is held low, as determined by Codec8,
1 Multiple bytes are transferred while maintaining SS low, up to and including the next byte read from the Tx
Other modes. Reserved.
Enable Output Buffer.
0 The output buffer for the 5 PSC pads are enabled if the TX or the RX part was enabled.
1 The output buffer for the 5 PSC pads is enabled independent from the transmitter or receiver.
Codec16, Codec24, or Codec32 selected by SICR[SIM].
FIFO that has its EOF flag set.
Table 25-26. SICR field descriptions (continued)
MPC5125 Microcontroller Reference Manual, Rev. 2
Description
Programmable Serial Controller (PSC)
25-31