MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 781

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

28.3.2.3
Refer to
The high frequency input clock, SDHC_CLK, derives the low frequency clock (CLK_20M) the card uses.
The divide circuitry consists of a 4-bit divider followed by a 12-bit prescaler. The SDHC_CLK is first
divided by the 4-bit divider to derive the signal, CLK_DIV. The 12-bit prescaler divides the CLK_DIV to
derive CLK_20M, which the card can use.
CLK_20M is used internally by the SDHC.
Figure 28-4
Freescale Semiconductor
Address: Base + 0x08
TIME_OUT_
TIME_OUT_
Reset
Reset
RESP
READ
Field
W
W
R
R
Section 28.4.7, “System Clock Controller,”
16
0
0
0
0
shows the SDHC_CLK_RATE register and
SDHC Clock Rate (SDHC_CLK_RATE) Register
Time Out Response. This indicates command response was not received in time specified in the
SDHC_RES_TO register. This can be caused by:
Writing a 1 to this bit clears this condition.
0 No error.
1 Time out response error occurred.
Time Out Read. Indicates expected data from the card was not received in time specified in the
SDHC_READ_TO register. The TIME_OUT_READ bit is cleared by an internal status change or by removing
the source of the error. Writing a 1 to this bit clears this bit.
0 No error.
1 Time out read data error occurred.
• An unsupported command received at the card(s)
• Another MMC/SD_OP_COND command submitted after all cards had already sent their voltage ranges
• An identification command issued when all cards are already in standby state
• No card is on the bus
17
0
0
0
1
and the power-up routine is finished
18
0
0
0
2
Figure 28-4. SDHC Clock Rate (SDHC_CLK_RATE) Register
Table 28-5. SDHC_STATUS field descriptions (continued)
19
0
0
0
3
MPC5125 Microcontroller Reference Manual, Rev. 2
20
4
0
0
0
CLK_PRESCALER
21
0
0
0
5
22
0
0
0
6
for the clock scheme.
23
0
0
0
7
Description
Table 28-6
24
8
0
0
0
25
9
0
0
0
describes the bit fields.
10
26
0
0
0
Secure Digital Host Controller (SDHC)
11
27
0
0
0
12
28
0
0
1
Access: User read/write
CLK_DIVIDER
13
29
0
0
0
14
30
0
0
0
15
31
28-9
0
0
0