MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 204

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

CSB Arbiter and Bus Monitor
8.2.1.2
Arbiter timers register (ATR) defines the arbiter address time out (ATO), data time out (DTO) timer’s
values.
8-4
Address: Base + 0x04
Reset
Reset
RPTCNT
WPARK
PARKM
APARK
Field
W
W
R
R
Figure 8-2
16
1
1
0
Arbiter Timers Register (ATR)
Repeat count. Specifies the maximum number of consecutive transactions, that any master can perform,
using REPEAT request mode.
000 1 consecutive transactions (REPEAT request mode disable)
001 2 consecutive transactions
010 3 consecutive transactions
011 4 consecutive transactions
100 5 consecutive transactions
101 6 consecutive transactions
110 7 consecutive transactions
111 8 consecutive transactions
Note: It is recommended not to program this field for more than 4 consecutive transactions.
WOP Parking. Specifies, whether bus is parked to CPU on WOP cycle (cycle after ARTRY assertion).
0 Park to CPU
1 Do not park bus to any master at WOP cycle
Address parking. Specifies arbiter bus parking mode.
00 Park to master. Arbiter parks the address bus to the master, that is selected by numeric value of PARKM
01 Park to last owner. Arbiter parks the address bus to last bus owner.
10 Disable. Arbiter does not assert BG to any master, if no BR is present.
11 Reserved
Parking master.
0000
0001
0010
0011–1111 Reserved
17
1
1
1
field.
shows the fields of ATR.
18
1
1
2
Power Architecture Core
Reserved
SAP
19
1
1
3
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 8-2. ACR field descriptions (continued)
Figure 8-2. Arbiter Timers Register (ATR)
20
4
1
1
21
1
1
5
22
1
1
6
23
1
1
7
Description
DTO
ATO
24
8
1
1
25
9
1
1
10
26
1
1
11
27
1
1
12
28
1
1
Freescale Semiconductor
Access: User read/write
13
29
1
1
14
30
1
1
15
31
1
1