MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 251

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 9-29
Freescale Semiconductor
DLAST_SGA[31:0] Last destination address adjustment or the memory address for the next transfer control descriptor to be
Address: Base + 0x1000 + (32 × n) + 0x0018
Address: Base + 0x1000 + (32 × n) + 0x001C
Reset
Reset
Reset
Reset
W
W
Field
W
W
R
R
R BITER.
R
See
See
E_LINK
—
—
—
—
16
16
0
0
and
BWC
Table 9-1
Table 9-1
—
—
Table 9-29
—
—
17
17
1
1
loaded into this channel (scatter/gather)
If TCD.e_sg equals 0,
Adjustment value is added to the destination address at the completion of the outer major iteration count.
This value can be applied to restore the destination address to the initial value or adjust the address to
reference the next data structure.
or
This address points to the beginning of a 0-modulo-32 region containing the next transfer control descriptor
to be loaded into this channel. This channel reload is performed as the major iteration count completes.
The scatter/gather address must be 0-modulo-32 or a configuration error is reported.
and
and
Figure 9-29. TCDn Word 7 (TCDn.{BITER,control/status}) Fields
—
—
—
—
18
18
2
2
BITER.LINKCH[5:0]
Table
Table
BITER[14:9] or
define word 7 of the TCDn structure, the BITER and control/status fields.
—
19
—
—
19
—
3
3
9-21.
Figure 9-28. TCDn Word 6 (TCDn.DLAST_SGA)
9-21.
MAJOR.LINKCH[5:0]
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 9-28. TCDn Word 6 field descriptions
—
—
—
—
20
20
4
4
—
—
—
—
21
21
5
5
—
—
—
—
22
22
6
6
DLAST_SGA[31:16]
DLAST_SGA[15:00]
—
—
—
—
23
23
7
7
Description
DONE
—
—
—
—
24
24
8
8
TIVE
AC
—
—
—
—
25
25
9
9
MAJOR.
E_LINK
—
—
—
—
10
26
10
26
BITER[8:0]
E_SG D_REQ
—
—
—
—
11
27
11
27
Direct Memory Access (DMA)
—
—
—
—
12
28
12
28
Access: User read/write
Access: User read/write
HALF
INT_
—
—
—
—
13
29
13
29
INT_
MAJ
—
—
—
—
14
30
14
30
START
—
—
—
—
15
31
15
31
9-31