MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 257

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

These settings generate the following sequence of events:
The DMA becomes idle or services the next channel.
9.3.4.2
The next example is the same as previous with the exception of transferring 32 bytes via two hardware
requests. The only fields that change are the major loop iteration count and the final address offsets. The
DMA is programmed for two iterations of the major loop transferring 16 bytes per iteration. After the
channel’s hardware requests are enabled in the DMAERQ register, channel service requests are initiated
by the slave device.
Freescale Semiconductor
1. IPS write to the TCD.START bit requests channel service.
2. The channel is selected by arbitration for servicing.
3. DMA_ENGINE writes: TCD.DONE = 0, TCD.START = 0, TCD.ACTIVE = 1.
4. DMA_ENGINE reads: channel TCD data from local memory to internal register file.
5. The source to destination transfers are executed as follows:
6. DMA_ENGINE writes: TCD.SADDR = 0x1000, TCD.DADDR = 0x2000, TCD.CITER = 1
7. DMA_ENGINE writes: TCD.ACTIVE = 0, TCD.DONE = 1, DMAINT[n] = 1.
8. The channel retires.
TCD.nbytes=16
TCD.saddr =0x1000
TCD.soff
TCD.ssize =0
TCD.slast =-16
TCD.daddr =0x2000
TCD.doff
TCD.dsize =2
TCD.dlast_sga=-16
TCD.int_maj =1
TCD.start =1
All other TCD fields = 0
a) READ_BYTE(0x1000), READ_BYTE(0x1001), READ_BYTE(0x1002),
b) WRITE_WORD(0x2000) → first iteration of the minor loop.
c) READ_BYTE(0x1004), READ_BYTE(0x1005), READ_BYTE(0x1006),
d) WRITE_WORD(0x2004) → second iteration of the minor loop.
e) READ_BYTE(0x1008), READ_BYTE(0x1009), READ_BYTE(0x100A),
f) WRITE_WORD(0x2008) → third iteration of the minor loop
g) READ_BYTE(0x100C), READ_BYTE(0x100D), READ_BYTE(0x100E),
h) WRITE_WORD(0x200C) → last iteration of the minor loop → major loop complete.
(TCD.BITER).
READ_BYTE(0x1003).
READ_BYTE(0x1007).
READ_BYTE(0x100B).
READ_BYTE(0x100F).
Multiple Requests
=1
=4
(TCD.word7 should be written last after all other fields have
MPC5125 Microcontroller Reference Manual, Rev. 2
been initialized)
Direct Memory Access (DMA)
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