MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 341

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

12.3.2.5
The Look-Up Table n Main Lower (LUT_TABLEn_MAIN_LOW) registers contain the lower eight
entries of the look-up tables for channels 0 to 4, main table. All registers contain identical fields.
Freescale Semiconductor
Address: Base + 0x00A0 (LUT_TABLE0_MAIN_LOW)
PRIO7[3:0]
PRIO6[3:0]
PRIO5[3:0]
PRIO4[3:0]
PRIO3[3:0]
PRIO2[3:0]
PRIO1[3:0]
PRIO0[3:0]
Reset
Reset
Field
W
W
R
R
Base + 0x00A4 (LUT_TABLE1_MAIN_LOW)
Base + 0x00A8 (LUT_TABLE2_MAIN_LOW)
Base + 0x00AC (LUT_TABLE3_MAIN_LOW)
Base + 0x00B0 (LUT_TABLE4_MAIN_LOW)
16
0
0
0
Look-Up Table n Main Lower (LUT_TABLEn_MAIN_LOW) Registers
Figure 12-6. Look-Up Table n Main Lower (LUT_TABLEn_MAIN_LOW) Registers
Priority setting if seven ACKs for own channel counted
Priority setting if six ACKs for own channel counted
Priority setting if five ACKs for own channel counted
Priority setting if four ACKs for own channel counted
Priority setting if three ACKs for own channel counted
Priority setting if two ACKs for own channel counted
Priority setting if one ACK for own channel counted
Priority setting if zero ACKs for own channel counted
PRIO7[3:0]
PRIO3[3:0]
17
0
0
1
18
0
0
2
Table 12-6. LUT_TABLEn_MAIN_LOW field descriptions
19
0
0
3
MPC5125 Microcontroller Reference Manual, Rev. 2
20
4
0
0
PRIO6[3:0]
PRIO2[3:0]
21
0
0
5
22
0
0
6
23
0
0
7
Description
24
8
0
0
PRIO5[3:0]
PRIO1[3:0]
25
9
0
0
Multi-port DRAM Controller Priority Manager
10
26
0
0
11
27
0
0
12
28
0
0
Access: User read/write
PRIO4[3:0]
PRIO0[3:0]
13
29
0
0
14
30
0
0
15
31
12-9
0
0