MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 849

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

32.2.4.2
The USB Status (USB_USBSTS) register indicates various states of each module and any pending
interrupts. This register does not indicate status resulting from a transaction on the serial bus. Software
clears certain bits in this register by writing a 1 to them.
Freescale Semiconductor
Address: Base + 0x144
Reset
Reset
Field
RS
W
W
R
R
AS
16
0
0
0
0
USB Status (USB_USBSTS) Register
Run/Stop.
Host Mode:
When set to a 1, the controller proceeds with the execution of the schedule. The controller continues execution
as long as this bit is set to 1. When this bit is set to 0, the host controller completes the current transaction on
the USB and then halts. The HC halted bit in the status register indicates when the host controller has finished
the transaction and has entered the stopped state. Software should not write a 1 to this field unless the
controller is in the halted state (i.e., HCHalted in the USB_USBSTS register is a 1).
Device Mode:
Writing a 1 to this bit causes the OTG controller to enable a pull-up on D+ and initiate an attach event. This
control bit is not directly connected to the pull-up enable, as the pull-up becomes disabled upon transitioning
into high-speed mode. Software should use this bit to prevent an attach event before the OTG controller has
been properly initialized. Writing a 0 to this causes a detach event.
0 Stop.
1 Run.
PS
17
0
0
0
1
RCL
18
0
0
0
2
Table 32-16. USB_USBCMD field descriptions (continued)
HCH
Figure 32-17. USB Status (USB_USBSTS) Register
19
0
0
0
3
MPC5125 Microcontroller Reference Manual, Rev. 2
20
4
0
0
0
0
ULPII
w1c
21
0
0
0
5
w1c
TI1
22
0
0
0
6
w1c
w1c
TI0
SLI
23
0
0
7
Description
w1c
SRI
24
8
0
0
0
w1c
URI
25
9
0
0
0
Universal Serial Bus Interface with On-The-Go
w1c
AAI
10
26
0
0
0
w1c
SEI
11
27
0
0
0
w1c
w1c
UPI
FRI
12
28
0
0
Access: User read/write
w1c
w1c
UAI
PCI
13
29
0
0
w1c
UEI
14
30
0
0
0
NAKI
32-21
w1c
UI
15
31
0
0