MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 391

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

The following describes the FEC RISC initialization operations specific to the FEC.
14.4.1.2
After asserting the ETHER_EN bit of the ETH_ECNTRL register, software can set up the buffer/frame
descriptors and write to the ETH_X_DES_ACTIVE and ETH_R_DES_ACTIVE registers.
14.5
14.5.1
The data for the FEC frames must reside in memory external to the FEC. The data for a frame is placed in
one or more buffers. A buffer descriptor (BD) that contains a starting address (pointer) and data length for
the buffer is associated with each buffer. In addition to pointing to the buffer, the most significant bit of
the BD is an ownership bit, which defines the current state of the buffer. Other bits in the buffer descriptor
are used to communicate status/control information between the Ethernet MAC and the driver. To permit
maximum user flexibility, the BDs used by the FEC DMA engineers also located in external memory.
Software produces buffers by allocating/initializing memory and initializing buffer descriptors. Setting the
R/E (ownership) bit in the most significant word of the transmit (receive) buffer descriptor produces the
buffer. A software write to either the ETH_X_DES_ACTIVE or the ETH_R_DES_ACTIVE register tells
the FEC that a buffer has been placed in external memory for the transmit or receive data traffic,
respectively. The hardware reads the BDs and consumes the buffers after they have been produced. After
the data DMA is complete and the buffer descriptor status bits have been written by the DMA engine, the
R(E) bit is cleared by hardware to signal the buffer has been consumed. Software may poll the BDs to
detect when the buffers have been consumed or may rely on the buffer/frame interrupts. These buffers may
then be processed by the driver and returned to the free list.
The ETHER_EN signal operates as a reset to the BD/DMA logic. When ETHER_EN is deasserted, the
DMA engine BD pointers are reset to point to the starting transmit and receive BDs. The buffer descriptors
are not initialized by hardware during reset. At least one transmit and receive buffer descriptor must be
initialized by software (write 0x0000_0000 to the most significant word of buffer descriptor) before the
ETHER_EN bit is set.
Freescale Semiconductor
1. Clear transmit FIFO.
2. Clear receive FIFO.
3. Initialize receive ring pointer.
4. Initialize transmit ring pointer.
5. Initialize FIFO count registers.
X_LAG, X_READ, X_WRITE
R_LAG, R_READ, R_WRITE
RDES_ADDR = ETH_R_DES_START
XDES_ADDR = ETH_X_DES_START
R_COUNT
Buffer Descriptors
Driver/DMA Operation with Buffer Descriptors
Initialization (After Asserting ETHER_EN)
=
X_COUNT
MPC5125 Microcontroller Reference Manual, Rev. 2
=
0
=
=
ETH_R_FSTART
0
Fast Ethernet Controller (FEC)
14-35