MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 573

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

21.3.2.2
During data tenure, the following occurs:
The ACK input signal is internally synchronized to the internal clock. At the first LPC clock edge where
the ACK input is detected as asserted, the LPC terminates the transaction and releases the bus on the next
LPC bus clock.
Figure 21-31
influence of register settings can be found in the MPC5125 Microcontroller Data Sheet.
Freescale Semiconductor
•
•
When a write to the device occurs, the LPC drives the indicated AD bits.
When a read occurs, the indicated AD bits are tri-stated by the LPC.
Data Tenure
show muxed burst transactions. Detailed information about timing diagrams and the
AD[0] is treated as the least significant data bit. Any unused data bits (as
indicated by the data size field in the associated control register) are driven
low by the LPC. Therefore, they should not be driven by the device or glue
chip.
In the following diagrams, deadcycle and holdcycle are each set to 0.
Figure 21-29
shows a muxed transaction-type timing diagram.
MPC5125 Microcontroller Reference Manual, Rev. 2
NOTE
NOTE
Figure 21-30
LocalPlus Bus Controller (LPC)
and
21-33