MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 887

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Split transaction interrupt, bulk and control are also managed using queue heads and queue element
transfer descriptors.
The periodic frame list is a 4K-page aligned array of frame list link pointers. The length of the frame list
may be programmable. The programmability of the periodic frame list is exported to system software via
the USB_HCCPARAMS register. If non-programmable, the length is 1024 elements. If programmable,
system software can select the length as one of 256, 512, or 1024 elements. An implementation must
support all three sizes. Programming the size (that is, the number of elements) is accomplished by system
software writing the appropriate value into frame list size field in the USB_USBCMD register.
Frame list link pointers direct the host controller to the first work item in the frame’s periodic schedule for
the current micro-frame. The link pointers are aligned on doubleword boundaries within the frame list.
Figure 32-44
Frame list link pointers always reference memory objects that are 32-byte aligned. The referenced object
may be an isochronous transfer descriptor for high-speed devices, a split-transaction isochronous transfer
descriptor (for full-speed isochronous endpoints), or a queue head (used to support high-, full- and
low-speed interrupt). System software should not place non-periodic schedule items into the periodic
schedule. The least significant bits in a frame list pointer key the host controller as to the type of object the
pointer is referencing.
The least significant bit is the T-Bit (bit 0). When this bit is set, the host controller never uses the value of
the frame list pointer as a physical memory pointer. The Typ field is used to indicate the exact type of data
structure referenced by this pointer. The value encodings for the Typ field are given in
Freescale Semiconductor
31
USB_PERIODICLISTBASE
USB_FRINDEX
Operational
Periodic Frame
Registers
List Element
shows the format for the frame list link pointer.
Address
1024, 512, or 256
MPC5125 Microcontroller Reference Manual, Rev. 2
Elements
Figure 32-43. Periodic Schedule Organization
Figure 32-44. Frame List Link Pointer Format
Frame List Link Pointer
Periodic Frame List
•
•
•
Poll Rate: N –– > 1
•
•
•
Universal Serial Bus Interface with On-The-Go
A
A
A
A
A
A
Isochronous Transfer
Descriptor(s)
8
Interrupt Queue
A
4
Heads
• • •
5
Table
4
00
1
32-43.
3
Last
Periodic has
End of
List Mark
2
Typ
1
32-59
T
0