MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 97

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Freescale Semiconductor
Address: Base + 0x10
EXT1HRS
Reset
Reset
SWSR
SWHR
SWRS
CSHR
PURS
JPRS
JHRS
JSRS
Field
W
W
R
R
16
0
0
0
0
0
Software soft reset. If set, indicates that a software soft reset has occurred. SWSR is cleared by writing a logic
1 to it.
Software hard reset. If set, indicates that a software hard reset has occurred. SWHR is cleared by writing a
logic 1 to it.
JTAG POReset status. When the JTAG reset (command) request is set, JPRS is set and remains set until
software clears it. JPRS is cleared by writing a logic 1 to it.
0 No JTAG reset event occurred.
1 A JTAG reset event occurred.
JTAG HReset status. When the JTAG reset (command) request is set, JHRS is set and remains set until
software clears it. JHRS is cleared by writing a logic 1 to it.
0 No JTAG reset event occurred.
1 A JTAG reset event occurred.
JTAG SReset status. When the JTAG reset (command) request is set, JSRS is set and remains set until
software clears it. JSRS is cleared by writing a logic 1 to it.
0 No JTAG reset event occurred.
1 A JTAG reset event occurred.
PLL Unlock reset status. PURS is cleared by writing a logic 1 to it.
0 No System PLL unlock event has occurred.
1 System PLL unlock event has occurred.
External HRESET1 status. EXT1HRS is cleared by writing a logic 1 to it.
0 No external HRESET1 event has occurred.
1 External HRESET1 event has occurred.
Check stop reset status. When the core enters a checkstop state and the checkstop reset is enabled by the
RMR[CSRE]. CSHR is cleared by writing a logic 1 to it.
0 No enabled check stop reset event occurred.
1 An enabled check stop reset event occurred.
Software watchdog reset status. When a software watchdog expire event (which causes a reset) is detected,
the SWRS bit is set and remains that way until the software clears it. SWRS is cleared by writing a logic 1 to it.
0 No software watchdog reset event occurred.
1 A software watchdog reset event has occurred.
17
0
1
0
0
1
SWSR SWHR
w1c
18
0
1
0
2
w1c
19
0
0
0
3
MPC5125 Microcontroller Reference Manual, Rev. 2
Figure 4-4. Reset Status Register (RSR)
20
4
0
0
0
0
Table 4-10. RSR field descriptions
JPRS JHRS JSRS PURS
w1c
21
0
0
0
5
w1c
22
0
0
0
6
w1c
23
0
0
0
7
Description
w1c
24
8
0
0
0
EXT1
HRS
w1c
25
9
0
0
0
10
26
0
0
0
0
CSHR SWRS BMRS SRS
w1c
11
27
0
0
0
w1c
12
28
0
0
0
Access: User read/write
w1c
13
29
0
0
0
w1c
14
30
0
0
0
HRS
w1c
Reset
15
31
4-11
0
0
0