MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 185

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

transmission or if a transmitter underrun occurs when the user fails to service the TDRE interrupt in a
timely manner. If a loss of arbitration occurs while the Type 3 IFR is being transmitted, transmission halts
immediately and the loss of arbitration is indicated in the BDLC_DLCBSVR register.
6.4.7.6
While the design of the BDLC module makes the transmission of each type of IFR similar, the steps
necessary for sending each is discussed. Again, a discussion of the bytes making up any particular IFR is
not within the scope of this document. For a more detailed description of the use of IFRs on an SAE J1850
network, refer to the SAE J1850 document.
6.4.7.6.1
To transmit a Type 1 IFR, the user loads the byte to be transmitted into the BDLC Data Register and sets
both the TSIFR bit and the TEOD bit. This directs the BDLC module to attempt transmitting the byte
written to the BDLC Data Register one time, preceded by the appropriate Normalization Bit. If the
transmission is not successful, the byte is discarded and no further transmission attempts are made. For an
illustration of the steps described below, refer to
Freescale Semiconductor
1. Load the IFR byte into the BDLC data register.
The user begins initiation of a Type 1 IFR by loading the desired IFR byte into the BDLC Data
Register. If a byte has already been written into the BDLC Data Register for transmission as a new
message, the user can simply write the IFR byte to the BDLC Data Register, replacing the
previously written byte. This must be done before the first EOD symbol is received.
Transmitting An IFR with the BDLC module
The TMIFR0 bit should not be used to transmit a Type 1 IFR. If a loss of
arbitration occurs on the last bit of a byte being transmitted using the
TMIFR0 bit, two extra logic ones are transmitted to ensure that the IFR does
not end on a byte boundary. This can cause an error in a Type 1 IFR.
Transmitting a Type 1 IFR
MPC5125 Microcontroller Reference Manual, Rev. 2
Figure
NOTE
6-22.
Byte Data Link Controller (BDLC)
6-49