MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 253

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Freescale Semiconductor
MAJOR.E_LINK
INT_HALF
INT_MAJ
ACTIVE
D_REQ
START
DONE
E_SG
Field
Enable channel-to-channel linking on major loop complete. As the channel completes the outer major
Channel done. This flag indicates the DMA has completed the outer major loop. It is set by the
DMA_ENGINE as the CITER count reaches 0; it is cleared by software or the hardware when the channel
is activated.
This bit must be cleared to write the MAJOR.E_LINK or E_SG bits.
Channel active. This flag signals the channel is currently in execution. It is set when channel service
begins, and is cleared by the DMA_ENGINE as the inner minor loop completes or if any error condition
is detected.
loop, this flag enables the linking to another channel, defined by MAJOR.LINKCH[5:0]. The link target
channel initiates a channel service request via an internal mechanism that sets the TCD.START bit of the
specified channel. To support the dynamic linking coherency model, this field is forced to zero when
written to while the TCD.DONE bit is set.
0 The channel-to-channel linking is disabled.
1 The channel-to-channel linking is enabled.
Enable scatter/gather processing. As the channel completes the outer major loop, this flag enables
scatter/gather processing in the current channel. If enabled, the DMA_ENGINE uses DLAST_SGA as a
memory pointer to a 0-modulo-32 address containing a 32-byte data structure that is loaded as the
transfer control descriptor into the local memory. To support the dynamic scatter/gather coherency model,
this field is forced to zero when written to while the TCD.DONE bit is set.
0 The current channel’s TCD is normal format.
1 The current channel’s TCD specifies a scatter gather format. The DLAST_SGA field provides a
Disable request. If this flag is set, the DMA hardware automatically clears the corresponding DMAERQ
bit when the current major iteration count reaches zero.
0 The channel’s DMAERQ bit is not affected.
1 The channel’s DMAERQ bit is cleared when the outer major loop is complete.
Enable an interrupt when major counter is half complete. If this flag is set, the channel generates an
interrupt request by setting the appropriate bit in the DMAINT register when the current major iteration
count reaches the halfway point. Specifically, the comparison performed by the DMA_ENGINE is (CITER
== (BITER >> 1)). This halfway point interrupt request is provided to support double-buffered schemes or
other types of data movement where the processor needs an early indication of the transfer’s progress.
The halfway complete interrupt is disabled when BITER values are less than 2.
0 The half-point interrupt is disabled.
1 The half-point interrupt is enabled.
Enable an interrupt when major iteration count completes. If this flag is set, the channel generates an
interrupt request by setting the appropriate bit in the DMAINT register when the current major iteration
count reaches 0.
0 The end-of-major loop interrupt is disabled.
1 The end-of-major loop interrupt is enabled.
Channel start. If this flag is set, the channel is requesting service. The DMA hardware automatically
clears this flag after the channel begins execution.
0 The channel is not explicitly started.
1 The channel is explicitly started via a software initiated service request.
memory pointer to the next TCD to be loaded into this channel after the outer major loop completes its
execution.
Table 9-29. TCDn Word 7 field descriptions (continued)
MPC5125 Microcontroller Reference Manual, Rev. 2
Description
Direct Memory Access (DMA)
9-33