MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 934

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Universal Serial Bus Interface with On-The-Go
transaction, the data toggle bit (dt) is toggled, the current page offset is advanced to the next appropriate
value (e.g., advanced by the number of bytes successfully moved), and the C_Page field is updated to the
appropriate value (if necessary). See
qTDs.”
The total bytes to transfer field may be zero when all the other criteria for executing a transaction are met.
When this occurs, the host controller executes a zero-length transaction to the endpoint. If the PID_Code
field indicates an IN transaction and the device delivers data, the host controller detects a packet babble
condition, set the babble and halted bits in the Status field, set the Active bit to a zero, write back the results
to the source qTD, then exit this state.
In the event an IN token receives a data PID mismatch response, the host controller must ignore the
received data (i.e., not advance the transfer state for the bytes received). Additionally, if the endpoint is an
interrupt IN, then the host controller must record that the transaction occurred (i.e., decrement
qHTransactionCounter). It is recommended (but not required) the host controller continue executing
transactions for this endpoint if the resultant value of qHTransactionCounter is greater than one.
If the response to the IN bus transaction is a Nak (or Nyet) and RL is non-zero, NakCnt is decremented by
one. If RL is zero, then no write-back by the host controller is required (for a transaction receiving a Nak
or Nyet response and the value of CErr did not change). Software should set the RL field to zero if the
queue head is an interrupt endpoint. Host controller hardware is not required to enforce this rule or
operation.
After the transaction has finished and the host controller has completed the post processing of the results
(advancing the transfer state and possibly NakCnt, the host controller writes back the results of the
transaction to the queue head’s overlay area in main memory.
The number of bytes moved during an IN transaction depends on how much data the device endpoint
delivers. The maximum number of bytes a device can send is Maximum Packet Size. The number of bytes
moved during an OUT transaction is either Maximum Packet Length bytes or Total Bytes to Transfer,
whichever is less.
If there was a transaction error during the transaction, the transfer state (as defined above) is not advanced
by the host controller. The CErr field is decremented by one and the status field is updated to reflect the
type of error observed. Transaction errors are summarized in
The following events causes the host controller to clear the Active bit in the queue head’s overlay status
field. When the Active bit transitions from a 1 to a 0, the transfer in the overlay is considered complete.
The reason for the transfer completion (clearing the Active bit) determines the next state.
32-106
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CErr field decrements to 0. When this occurs the Halted bit is set to a one and Active is set to a
zero. This results in the hardware not advancing the queue and the pipe halts. Software must
intercede to recover.
The device responds to the transaction with a STALL PID. When this occurs, the Halted bit is set
to a one and the Active bit is set to a zero. This results in the hardware not advancing the queue and
the pipe halts. Software must intercede to recover.
The Total Bytes to Transfer field is zero after the transaction completes. For a zero length
transaction, it was zero before the transaction was started. When this condition occurs, the Active
bit is set to zero.
MPC5125 Microcontroller Reference Manual, Rev. 2
Section 32.6.9.6, “Buffer Pointer List Use for Data Streaming with
Section 32.6.14.1.1, “Transaction Error.”
Freescale Semiconductor