MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 190

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Byte Data Link Controller (BDLC)
6-54
1. Load the first IFR byte into the BDLC data register.
2. Set the TMIFR bit.
3. When TDRE is indicated, write the next IFR byte into the BDLC data register.
4. Write the last IFR byte into the BDLC data register and set TEOD.
The user begins initiation of a Type 3 IFR, as with each of the other IFR types, by loading the
desired IFR byte into the BDLC Data Register. If a byte has already been written into the BDLC
Data Register for transmission as a new message, the user can simply write the first IFR byte to the
BDLC Data Register, replacing the previously written byte. This must be done before the first EOD
symbol is received.
The second step necessary for transmitting a Type 3 IFR is to set the desired TMIFR bit in BDLC
Control Register 2, depending upon whether or not a CRC is desired. As previously described in
Section 6.4.7.2, “BDLC IFR Transmit Control Bits,”
requires a CRC byte to be appended following the last byte of the Type 3 IFR, and TMIFR0 if no
CRC byte is required.
Setting the TMIFR1 or TMIFR0 bit directs the BDLC module to transmit the byte in the BDLC
Data Register as the first byte of a single or multi-byte IFR preceded by the appropriate
Normalization Bit. After this has occurred, the BDLC_DLCBSVR register reflects that the next
byte of the IFR can be written to the BDLC Data Register (TDRE interrupt).
When a TDRE state is reflected in the BDLC_DLCBSVR register, the CPU writes the next IFR
byte to be transmitted into the BDLC Data Register, clearing the TDRE interrupt. This step is
repeated until the last IFR byte to be transmitted is written to the BDLC Data Register.
After the last IFR byte to be transmitted is written to the BDLC Data Register, the CPU then sets
the TEOD bit in BDLC Control Register 2. After the TEOD bit is set and the last IFR byte written
to the BDLC Data Register is transmitted onto the bus (if the TMIFR1 bit has been set), the BDLC
module begins transmitting the CRC byte, followed by an EOD. If the TMIFR0 bit has been set,
the last IFR byte is immediately followed by the transmission of an EOD. Following the EOD, EOF
is recognized and the message is complete.
If a loss of arbitration occurs at any time during the transmission of a Type 3 IFR, the TMIFR bit
is set, and the TEOD bit (if set) is cleared, any IFR byte being transmitted is discarded and the loss
of arbitration state is reflected in the BDLC_DLCBSVR register. Likewise, if an error is detected
The user must set the TMIFR1 or TMIFR0 bit before the EOD following the
main part of the message frame is received or no IFR transmit attempts are
made for the current message. If another node does transmit an IFR to this
message or a reception error occurs, the TMIFR1 or TMIFR0 bit is cleared.
If not, the IFR is transmitted after the EOD of the next received message.
When transmitting a Type 3 IFR, you may write two or three of the bytes to
be transmitted into the BDLC Data Register before the first Rx IFR interrupt
occurs. For this reason, never use receive IFR byte interrupts to control the
sequencing of IFR bytes to be transmitted.
MPC5125 Microcontroller Reference Manual, Rev. 2
NOTE
NOTE
the TMIFR1 bit should be set if the user
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